fpga -磁力猫 -最好用的磁力搜索引擎

[压缩文件] [ FreeCourseWeb.com ] Udemy - FPGA Embedded Design, Part 2 - Basic FPGA Training.zip

[ FreeCourseWeb.com ] Udemy - FPGA Embedded Design, Part 2 - Basic FPGA Training.zip 1.4 GB

[磁力链接] 添加时间:2021-06-02 大小:1.4 GB 最近下载:2025-05-12 热度:6581

[文档书籍] HDL Books - VHDL FPGA CPLD Verilog Digital Electronics eBook

0131972553 - (2005) Digital Fundamentals.pdf 492.0 MB
0126912955 - (2000) Engineering Digital Design.pdf 50.6 MB
0792397460 - (1996) LOGIC SYNTHESIS AND VERIFICATION ALGORITHMS.pdf 41.7 MB
0965193438 - (1996) HDL Chip Design- A Practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs Using VHDL or Verilog.pdf 40.6 MB
0471720925 - (2006) RTL Hardware Design Using VHDL Coding for Efficiency, Portability, and Scalability.pdf 35.8 MB
0072460857 - (2005) Fundamentals of Digital Logic with VHDL Design.pdf 35.6 MB
0132543036 - (2011) Digital Electronics - A Practical Approach with VHDL - 9th Edition.pdf 33.6 MB
0470828498 - (2011) Design for Embedded Image Processing on FPGAs.pdf 28.7 MB
0070471649 - (1999) Verilog Digital System Design.pdf 28.3 MB
0134516753 - (1996) Verilog HDL A Guide to Digital Design and Synthesis B.pdf 22.4 MB
0470185317 - (2008) FPGA Prototyping by VHDL Examples - Xilinx Spartan-3 Version.pdf 22.3 MB
0131543180 - (2005) Practical FPGA Programming in C.chm 18.2 MB
1402055293 - (2007) Processor Design System-On-Chip Computing for ASICs and FPGAs.pdf 15.6 MB
0387284850 - (2006) FPGA Implementations of neural networks.pdf 14.7 MB
0136507638 - (1996) VHDL Made Easy.pdf 13.8 MB
0412616505 - (1997) VHDL A logic synthesis approach.pdf 13.4 MB
1934404055 - (2007) Digital Circuit Analysis and Design with Simulink Modeling and Introduction to CPLDs and FPGAs 2nd Ed.pdf 13.4 MB
0077221435 - (2008) Fundamentals of Digital Logic with VHDL Design - Ed. 3.pdf 12.8 MB
0792395980 - (1995) VHDL Coding Styles and Methodologies.pdf 12.7 MB
0123744385 - (2009) Low-Power Design of Nanometer FPGAs Architecture and EDA.pdf 12.6 MB

[磁力链接] 添加时间:2020-02-03 大小:1.2 GB 最近下载:2025-05-13 热度:14366

[其他] Learn VHDL and FPGA Development with a BASYS 3

Learn VHDL and FPGA Development with a BASYS 3.tgz 1.7 GB
Torrent Downloaded From ExtraTorrent.cc.txt 352 Bytes
Torrent downloaded from demonoid.pw.txt 46 Bytes

[磁力链接] 添加时间:2020-02-05 大小:1.7 GB 最近下载:2025-05-11 热度:7337

[其他] FPGA Design Learning VHDL

FPGA Design Learning VHDL.tgz 1.7 GB
Torrent Downloaded From ExtraTorrent.cc.txt 352 Bytes
Torrent downloaded from demonoid.pw.txt 46 Bytes

[磁力链接] 添加时间:2020-02-11 大小:1.7 GB 最近下载:2025-05-12 热度:8051

[影视] FPGA Development in VHDL - Beyond the Basics

03.Working with Custom Data Types/08.Demo.mp4 84.1 MB
06.Constructing State Machines/05.Demo - Combination Lock (Mealy).mp4 62.8 MB
05.Keeping Code Organized with Subprograms and Packages/05.Generics.mp4 50.4 MB
05.Keeping Code Organized with Subprograms and Packages/06.Resolution Functions.mp4 42.9 MB
06.Constructing State Machines/04.Demo - Traffic Lights (Moore).mp4 41.5 MB
07.Testing Your Designs/04.Testing with VUnit.mp4 30.8 MB
02.Developing for the FPGA/05.Demo - Compilation Report.mp4 26.8 MB
07.Testing Your Designs/03.A Sample Testbench.mp4 26.7 MB
02.Developing for the FPGA/07.Demo - MATLAB HDL Coder.mp4 23.5 MB
04.Monitoring Signal States with Attributes/04.Function Kind Attributes.mp4 15.8 MB
06.Constructing State Machines/06.State Encoding Styles.mp4 13.9 MB
05.Keeping Code Organized with Subprograms and Packages/03.Procedures.mp4 10.9 MB
03.Working with Custom Data Types/03.Arrays and Ranges.mp4 10.8 MB
07.Testing Your Designs/02.Testing and Testbenches.mp4 8.1 MB
04.Monitoring Signal States with Attributes/03.Value Kind Attributes.mp4 7.5 MB
03.Working with Custom Data Types/02.Standard Data Types Recap.mp4 6.5 MB
02.Developing for the FPGA/04.Compilation Process.mp4 5.6 MB
05.Keeping Code Organized with Subprograms and Packages/04.Constants.mp4 5.0 MB
04.Monitoring Signal States with Attributes/07.User-defined Attributes.mp4 4.5 MB
05.Keeping Code Organized with Subprograms and Packages/02.Design Unit Recap.mp4 4.4 MB

[磁力链接] 添加时间:2020-02-14 大小:541.2 MB 最近下载:2025-05-13 热度:14074

[影视] Getting Started with FPGA Programming with VHDL

07.Packages and Components/06.Demo - Packages and Components.mp4 48.3 MB
08.Debugging and Analysis/02.Simulation with ModelSim.mp4 43.4 MB
02.FPGA Technology Overview/04.A Look at the Development Board.mp4 39.9 MB
06.Writing Concurrent Code/07.Demo - Resettable Timer.mp4 39.2 MB
04.Introduction to VHDL/06.Interacting with Board IO.mp4 31.9 MB
05.Writing Sequential Code/08.Demo - Sequential Constructs.mp4 31.5 MB
02.FPGA Technology Overview/05.Setting up the EDA.mp4 20.5 MB
08.Debugging and Analysis/03.SignalTap Logic Analyzer.mp4 19.8 MB
02.FPGA Technology Overview/03.What Is an FPGA.mp4 16.9 MB
04.Introduction to VHDL/04.Ports and Board IO.mp4 15.5 MB
02.FPGA Technology Overview/06.Project Setup.mp4 13.2 MB
02.FPGA Technology Overview/08.Programming the FPGA.mp4 10.9 MB
02.FPGA Technology Overview/07.Pin Assignments and the Pin Planner.mp4 9.8 MB
01.Course Overview/01.Course Overview.mp4 9.2 MB
07.Packages and Components/02.The IEEE Library and Standard Logic.mp4 8.0 MB
03.Digital Design Primer/04.Addition and Multiplication.mp4 8.0 MB
05.Writing Sequential Code/05.More Data Types.mp4 7.3 MB
07.Packages and Components/04.Components and Port Maps.mp4 7.3 MB
03.Digital Design Primer/05.Flip-flop, MUX, and LUT.mp4 7.0 MB
03.Digital Design Primer/03.Logic Gates.mp4 7.0 MB

[磁力链接] 添加时间:2020-02-27 大小:520.8 MB 最近下载:2025-05-12 热度:19699

[影视] [udemy] Xilinx Vivado Beginners Course to FPGA Development in VHDL [MyFOM]

Section 2 Lab 1/Implementation of VHDL Design in Vivado and IO Pin Planning.mp4 72.5 MB
Section 4 Lab 3/Designing a Microblaze Soft Processor in Vivado IP Integrator.mp4 62.0 MB
Section 4 Lab 3/Learn VHDL by Example.mp4 60.0 MB
Section 3 Lab 2/Design a Block RAM in IP Integrator.mp4 53.0 MB
Section 2 Lab 1/Downloading the Bit-stream to the FPGA.mp4 48.5 MB
Section 2 Lab 1/Introduction to the Vivado Design Suite Interface and Creating a New Project.mp4 47.8 MB
Section 1 Introduction to Vivado/How to Download and Install Xilinx Vivado Design Suite.mp4 42.2 MB
Section 2 Lab 1/Coding and Simulating Simple VHDL in Vivado.mp4 36.2 MB
Section 3 Lab 2/Simulating BRAM memory IP in Vivado.mp4 23.3 MB
Section 4 Lab 3/Generating a Microblaze using TCL commands in Vivado.mp4 21.1 MB
Section 1 Introduction to Vivado/Introduction.mp4 16.9 MB
MyFreeOnlineMovies.co.uk.html 189.0 kB
Torrent Downloaded from Glodls.to.txt 237 Bytes
Section 4 Lab 3/New Text Document.txt 52 Bytes
Section 5 Conclusion and Bonus Section/Sorry the files are deleted bare with me.txt 51 Bytes

[磁力链接] 添加时间:2020-02-28 大小:483.8 MB 最近下载:2025-05-13 热度:6376

[影视] [FreeTutorials.Us] Udemy - Learn VHDL and FPGA Development

16. Lab 6 - Multiplier/2. BASYS 3 Multiplier Demonstration.mp4 107.3 MB
5. VHDL Coding Structure/3. VHDL Design Architecture Styles.mp4 102.2 MB
11. Lab 1 - Full Adder/2. BASYS 3 Full Adder Demonstration.mp4 92.1 MB
8. FPGA Development Boards/2. BASYS 3 Board Overview.mp4 88.5 MB
17. Lab 7 - RC Servo/2. BASYS 3 RC Servo Demonstration.mp4 85.6 MB
4. VHDL Syntax/2. If Statement Case Statement.mp4 79.9 MB
13. Lab 3 - Universal Shift Register/2. BASYS 3 Universal Shift Register Demonstration.mp4 74.1 MB
4. VHDL Syntax/3. For Loop While Loop.mp4 73.8 MB
13. Lab 3 - Universal Shift Register/4. BASYS 2 Universal Shift Register Solution.mp4 73.0 MB
13. Lab 3 - Universal Shift Register/3. BASYS 2 Universal Shift Register Demonstration.mp4 65.3 MB
16. Lab 6 - Multiplier/3. BASYS 2 Multiplier Demonstration.mp4 64.9 MB
5. VHDL Coding Structure/2. VHDL Design Structure.mp4 63.8 MB
4. VHDL Syntax/6. VHDL Processes and Concurrent Statement.mp4 58.4 MB
2. Introduction/2. Introduction to VHDL.mp4 58.0 MB
3. VHDL Data Types/3. Unsigned Signed Data Types.mp4 49.8 MB
12. Lab 2 - Shift Register/2. BASYS 3 Shift Register Demonstration.mp4 49.1 MB
6. Test Bench/1. Test Benches Introduction.mp4 48.6 MB
14. Lab 4 - 7 Segment Display/3. BASYS 2 - 7 Segment Display Demonstration.mp4 47.6 MB
14. Lab 4 - 7 Segment Display/2. BASYS 3 - 7 Segment Display Demonstration.mp4 46.0 MB
3. VHDL Data Types/2. Signals Variables Constants.mp4 43.6 MB

[磁力链接] 添加时间:2020-03-06 大小:2.1 GB 最近下载:2025-05-12 热度:3514

[压缩文件] Mentor FPGA

Mentor FPGA Advantage 8.1.iso 644.1 MB

[磁力链接] 添加时间:2020-03-18 大小:644.1 MB 最近下载:2024-12-20 热度:220

[影视] [UdemyCourseDownloader] Learning FPGA Development

5 - 4._Implementation/27. Xilinx_hardware_demo.mp4 22.6 MB
5 - 4._Implementation/26. Xilinx_implementation_demo.mp4 22.0 MB
5 - 4._Implementation/23. Intel_implementation_demo.mp4 13.9 MB
4 - 3._Hardware_Description_Languages/19. 4-bit_adder_simulation_example.mp4 13.1 MB
4 - 3._Hardware_Description_Languages/20. Sequential_logic_simulation_example.mp4 12.3 MB
5 - 4._Implementation/24. Intel_hardware_demo.mp4 12.3 MB
3 - 2._Embedded_Development_Process/09. FPGA_development_process_overview.mp4 9.8 MB
1 - Introduction/01. Get_your_digital_design_journey_started.mp4 9.0 MB
4 - 3._Hardware_Description_Languages/16. Verilog_primer.mp4 8.8 MB
3 - 2._Embedded_Development_Process/10. FPGA_families_and_development_boards.mp4 8.2 MB
2 - 1._Field_Programmable_Gate_Arrays/08. Other_blocks.mp4 7.8 MB
2 - 1._Field_Programmable_Gate_Arrays/06. Inside_an_FPGA_-_Logic_blocks.mp4 7.6 MB
4 - 3._Hardware_Description_Languages/15. Verilog_and_VHDL.mp4 7.1 MB
4 - 3._Hardware_Description_Languages/14. Digital_system_modeling.mp4 6.6 MB
Ex_Files_FPGA_Development.zip 5.6 MB
5 - 4._Implementation/25. Demo_system_for_the_Xilinx_platform.mp4 5.0 MB
5 - 4._Implementation/22. Demo_system_for_the_Intel_platform.mp4 4.4 MB
3 - 2._Embedded_Development_Process/11. Electronic_design_automation_tools.mp4 3.8 MB
2 - 1._Field_Programmable_Gate_Arrays/07. Inside_an_FPGA_-_Interconnects.mp4 3.4 MB
5 - 4._Implementation/21. FPGA_example_implementation_requirements.mp4 3.2 MB

[磁力链接] 添加时间:2020-03-19 大小:207.4 MB 最近下载:2025-05-12 热度:2341

[影视] [FreeTutorials.Us] Udemy - Learn VHDL and FPGA Development

16. Lab 6 - Multiplier/2. BASYS 3 Multiplier Demonstration.mp4 107.3 MB
5. VHDL Coding Structure/3. VHDL Design Architecture Styles.mp4 102.2 MB
11. Lab 1 - Full Adder/2. BASYS 3 Full Adder Demonstration.mp4 92.1 MB
8. FPGA Development Boards/2. BASYS 3 Board Overview.mp4 88.5 MB
17. Lab 7 - RC Servo/2. BASYS 3 RC Servo Demonstration.mp4 85.6 MB
4. VHDL Syntax/2. If Statement Case Statement.mp4 79.9 MB
13. Lab 3 - Universal Shift Register/2. BASYS 3 Universal Shift Register Demonstration.mp4 74.1 MB
4. VHDL Syntax/3. For Loop While Loop.mp4 73.8 MB
13. Lab 3 - Universal Shift Register/4. BASYS 2 Universal Shift Register Solution.mp4 73.0 MB
13. Lab 3 - Universal Shift Register/3. BASYS 2 Universal Shift Register Demonstration.mp4 65.3 MB
16. Lab 6 - Multiplier/3. BASYS 2 Multiplier Demonstration.mp4 64.9 MB
5. VHDL Coding Structure/2. VHDL Design Structure.mp4 63.8 MB
4. VHDL Syntax/6. VHDL Processes and Concurrent Statement.mp4 58.4 MB
2. Introduction/2. Introduction to VHDL.mp4 58.0 MB
3. VHDL Data Types/3. Unsigned Signed Data Types.mp4 49.8 MB
12. Lab 2 - Shift Register/2. BASYS 3 Shift Register Demonstration.mp4 49.1 MB
6. Test Bench/1. Test Benches Introduction.mp4 48.6 MB
14. Lab 4 - 7 Segment Display/3. BASYS 2 - 7 Segment Display Demonstration.mp4 47.6 MB
14. Lab 4 - 7 Segment Display/2. BASYS 3 - 7 Segment Display Demonstration.mp4 46.0 MB
3. VHDL Data Types/2. Signals Variables Constants.mp4 43.6 MB