fpga -磁力猫 -最好用的磁力搜索引擎

[压缩文件] FPGA

7010/ZedBoard/Ubuntu_zz_ftp_ssh_linux.7z 3.4 GB
7010/ZedBoard/视频教程发布/51,ZEDBOARD嵌入式LINUX平台搭建.rar 2.4 GB
7010/ZedBoard/ov7670采集以及显示系统详解以及实现2016_10_28.rar 1.7 GB
7010/EBAZ4205/ebit_linux/TF/pynq_z2_v2.4.zip 1.6 GB
7010/ZedBoard/视频教程发布/2，Zedboard上运行桌面LINUX.rar 1.2 GB
7010/EBAZ4205/ebit_linux/TF/xillinux-2.0.img.gz 1.2 GB
FPGA/4205启动xillinux系统/xillinux-2.0.img.gz 1.2 GB
7010/4205资料.zip 879.6 MB
ebaz4205-gathered-by-ustcpetergu.zip 801.8 MB
7010/ZedBoard/视频教程发布/22，SPI FLASH里启动LINUX的详细分析和实现.rar 688.1 MB
7010/ZedBoard/视频教程发布/8,建立LINUX开发环境并编译LINUX和UBOOT以及生成设备树.rar 646.9 MB
7010/ZedBoard/视频教程发布/16，MIO和EMIO下的GPIO分析和实例.rar 641.1 MB
7010/ZedBoard/视频教程发布/13，PL和PS协同设计实现对OLED的控制.rar 472.3 MB
7010/ZedBoard/视频教程发布/24，VGA接口原理分析以及控制逻辑的实现.rar 458.8 MB
7010/ZedBoard/视频教程发布/26，使用VIVADO例化BRAM实现VGA独立缓存驱动.rar 390.5 MB
7010/ZedBoard/视频教程发布/17，GPIO中断源的配置以及中断试验.rar 371.9 MB
7010/ZedBoard/视频教程发布/18，多路PWM原理分析以及实现试验.rar 346.2 MB
7010/ZedBoard/视频教程发布/25，纯PL实现独立显存VGA驱动并显示画面.rar 334.7 MB
7010/ZedBoard/视频教程发布/23，QT开发环境的建立以及在ZEDBOARD开发板上运行第一个QT例子.rar 317.1 MB
7010/ZedBoard/视频教程发布/12，学习使用VIO以及进行试验.rar 277.0 MB

[磁力链接] 添加时间:2024-01-21 大小:24.8 GB 最近下载:2025-05-04 热度:513

[压缩文件] FPGA

7010/ZedBoard/Ubuntu_zz_ftp_ssh_linux.7z 3.4 GB
7010/ZedBoard/视频教程发布/51,ZEDBOARD嵌入式LINUX平台搭建.rar 2.4 GB
7010/ZedBoard/ov7670采集以及显示系统详解以及实现2016_10_28.rar 1.7 GB
7010/EBAZ4205/ebit_linux/TF/pynq_z2_v2.4.zip 1.6 GB
7010/ZedBoard/视频教程发布/2，Zedboard上运行桌面LINUX.rar 1.2 GB
7010/EBAZ4205/ebit_linux/TF/xillinux-2.0.img.gz 1.2 GB
FPGA/4205启动xillinux系统/xillinux-2.0.img.gz 1.2 GB
7010/4205资料.zip 879.6 MB
ebaz4205-gathered-by-ustcpetergu.zip 801.8 MB
7010/ZedBoard/视频教程发布/22，SPI FLASH里启动LINUX的详细分析和实现.rar 688.1 MB
7010/ZedBoard/视频教程发布/8,建立LINUX开发环境并编译LINUX和UBOOT以及生成设备树.rar 646.9 MB
7010/ZedBoard/视频教程发布/16，MIO和EMIO下的GPIO分析和实例.rar 641.1 MB
7010/ZedBoard/视频教程发布/13，PL和PS协同设计实现对OLED的控制.rar 472.3 MB
7010/ZedBoard/视频教程发布/24，VGA接口原理分析以及控制逻辑的实现.rar 458.8 MB
7010/ZedBoard/视频教程发布/26，使用VIVADO例化BRAM实现VGA独立缓存驱动.rar 390.5 MB
7010/ZedBoard/视频教程发布/17，GPIO中断源的配置以及中断试验.rar 371.9 MB
7010/ZedBoard/视频教程发布/18，多路PWM原理分析以及实现试验.rar 346.2 MB
7010/ZedBoard/视频教程发布/25，纯PL实现独立显存VGA驱动并显示画面.rar 334.7 MB
7010/ZedBoard/视频教程发布/23，QT开发环境的建立以及在ZEDBOARD开发板上运行第一个QT例子.rar 317.1 MB
7010/ZedBoard/视频教程发布/12，学习使用VIO以及进行试验.rar 277.0 MB

[磁力链接] 添加时间:2021-01-25 大小:24.8 GB 最近下载:2025-05-12 热度:6314

[影视] [ DevCourseWeb.com ] Udemy - FPGA (Field-Programmable Gate Array) Design and Implementation

~Get Your Files Here !/03 - FPGA Design Flows & Design Tools/001 FPGA Design Flows & Design Tools.mp4 285.8 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/009 Design Examples.mp4 226.6 MB
~Get Your Files Here !/20 - Memristive FPGA/001 Memristive FPGA.mp4 215.6 MB
~Get Your Files Here !/12 - Reconfigurable Hardware/001 Reconfigurable Hardware.mp4 209.9 MB
~Get Your Files Here !/05 - Simulate and Implement SOPC Design/001 Simulate and Implement SOPC Design.mp4 198.1 MB
~Get Your Files Here !/01 - Introduction to FPGA (Field Programmable Gate Arrays)/001 Introduction to FPGA (Field Programmable Gate Arrays).mp4 192.1 MB
~Get Your Files Here !/21 - Mentor Graphics Tools & Guidelines/001 Mentor Graphics Tools & Guidelines.mp4 184.3 MB
~Get Your Files Here !/09 - Image Processing using FPGA/001 Image Processing using FPGA.mp4 179.7 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/006 Visual Verification of Designs.mp4 165.7 MB
~Get Your Files Here !/19 - Programmable Chips and Boards/001 Programmable Chips and Boards.mp4 163.7 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/008 Finite State Machines - part 2.mp4 153.1 MB
~Get Your Files Here !/14 - FPGA implementation of DSP Circuits/001 FPGA implementation of DSP Circuits.mp4 149.7 MB
~Get Your Files Here !/15 - Reversible Logic Circuits/001 Reversible Logic Circuits.mp4 143.4 MB
~Get Your Files Here !/07 - UART SDRAM Python/001 UART SDRAM Python.mp4 132.5 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/007 Finite State Machines - part 1.mp4 132.3 MB
~Get Your Files Here !/11 - Protoflex/001 Protoflex.mp4 123.6 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/004 Procedural Assignments.mp4 119.6 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/001 Introduction to FPGA Design using Verilog.mp4 115.5 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/002 Verilog overview.mp4 111.3 MB
~Get Your Files Here !/13 - Wordcount using MapReduce for FPGA/001 Wordcount using MapReduce for FPGA.mp4 109.6 MB

[磁力链接] 添加时间:2022-03-03 大小:4.3 GB 最近下载:2025-05-13 热度:7857

[影视] [ DevCourseWeb.com ] Udemy - High-Level Synthesis For Fpga, Part 3 - Advanced

~Get Your Files Here !/6 - Pointers/35 - MultiAccess Pointers on the Interface.mp4 260.9 MB
~Get Your Files Here !/9 - HLS Stream Library/55 - Stream on the Interface.mp4 194.9 MB
~Get Your Files Here !/9 - HLS Stream Library/56 - BlockingNonBlocking.mp4 185.4 MB
~Get Your Files Here !/2 - LAB Setup/5 - Linux Installation.mp4 180.1 MB
~Get Your Files Here !/7 - AXI in HLS/44 - The maxi interface.mp4 161.8 MB
~Get Your Files Here !/3 - MultiCycle Design/14 - BlockLevel Handshake.mp4 154.1 MB
~Get Your Files Here !/6 - Pointers/34 - Pointer Arithmetic.mp4 132.5 MB
~Get Your Files Here !/6 - Pointers/31 - Definition.mp4 128.2 MB
~Get Your Files Here !/7 - AXI in HLS/40 - Memory Mapped Output 01.mp4 127.5 MB
~Get Your Files Here !/3 - MultiCycle Design/9 - Example.mp4 125.2 MB
~Get Your Files Here !/3 - MultiCycle Design/12 - Example with ack.mp4 125.0 MB
~Get Your Files Here !/4 - Streaming/21 - Streaming Example Vivado.mp4 121.5 MB
~Get Your Files Here !/7 - AXI in HLS/43 - Memory Mapped IO.mp4 116.3 MB
~Get Your Files Here !/3 - MultiCycle Design/11 - Example with vld.mp4 112.4 MB
~Get Your Files Here !/6 - Pointers/33 - Pointers on the Interface.mp4 111.2 MB
~Get Your Files Here !/8 - Loops In HLS/48 - Loop Unrolling.mp4 110.3 MB
~Get Your Files Here !/5 - ArrayInHLS/28 - Array ReadWrite Vivado.mp4 110.0 MB
~Get Your Files Here !/7 - AXI in HLS/42 - Memory Mapped Output 02.mp4 100.3 MB
~Get Your Files Here !/6 - Pointers/32 - Native Pointer Casting.mp4 95.1 MB
~Get Your Files Here !/5 - ArrayInHLS/25 - Array Issues.mp4 92.1 MB

[磁力链接] 添加时间:2023-05-12 大小:4.0 GB 最近下载:2025-05-13 热度:3263

[影视] [ TutPig.com ] Udemy - Learn VHDL, PLS's and FPGA (Digital Electronic 2)

~Get Your Files Here !/12. Processor Design and its VHDL/1. Simple Processor Design and its VHDL.mp4 489.0 MB
~Get Your Files Here !/5. Multiplexers and Shannon Expansion/1. Multiplexers and Shannon Expansion.mp4 323.1 MB
~Get Your Files Here !/4. VHDL Adders Multiplier Narrated/1. VHDL for adders, Multiplier.mp4 308.1 MB
~Get Your Files Here !/11. VHDL code of the bus design with SWAP operation/1. VHDL code of the bus design with SWAP operation.mp4 238.9 MB
~Get Your Files Here !/3. Half Adders, Full Adders, RCA, CLA/1. HA FA RCA CLA.mp4 209.8 MB
~Get Your Files Here !/7. Conditional statement generate statement/1. Conditional statement, Generate statement, Sequential Assignment, VHDL operators.mp4 205.8 MB
~Get Your Files Here !/6. Decoders Arithmetic Comparator Selected signal assignment/1. Decoders, Arithmetic Comparator, Selected signal assignment.mp4 199.4 MB
~Get Your Files Here !/13. Modelsim/3. Modelsim Tutorial 2.mp4 198.7 MB
~Get Your Files Here !/9. VHDL gated latches flipflops, registers and counter/1. VHDL for Latches, FlipFlops, registers and counters.mp4 166.1 MB
~Get Your Files Here !/10. VHDL parallel load counters and bus design/1. Parallel Load counters and bus design.mp4 163.5 MB
~Get Your Files Here !/1. Introduction/1. Introduction to CAD tools.mp4 152.4 MB
~Get Your Files Here !/13. Modelsim/2. Modelsim Tutorial 1.mp4 134.6 MB
~Get Your Files Here !/8. latches flipflops shift and parallel access registers/1. Latches, FlipFlops, parallel access and shift registers.mp4 122.1 MB
~Get Your Files Here !/2. Numbers Representations & LUTs, PLDs, FPGA/2. LUTs, PLDs, FPGA.mp4 116.6 MB
~Get Your Files Here !/2. Numbers Representations & LUTs, PLDs, FPGA/1. Numbers Representations.mp4 93.2 MB
~Get Your Files Here !/1. Introduction/1.1 Fundamentals Of Digital Logic With VHDL Design 3rd Edition.pdf 12.8 MB
~Get Your Files Here !/4. VHDL Adders Multiplier Narrated/1.1 CENG335 Lecture 2 VHDL Adders Multiplier Narrated.pptx 3.4 MB
~Get Your Files Here !/3. Half Adders, Full Adders, RCA, CLA/1.1 CENG335 Lecture 3 HA FA RCA CLA.pptx 3.0 MB
~Get Your Files Here !/5. Multiplexers and Shannon Expansion/1.1 CENG335 Lecture 4 Multiplexers and Shannon Expansion.pptx 2.6 MB
~Get Your Files Here !/12. Processor Design and its VHDL/1.6 Exercises_set1_solution_part2.pdf 2.5 MB

[磁力链接] 添加时间:2021-12-08 大小:3.2 GB 最近下载:2025-05-12 热度:4791

[压缩文件] [ DevCourseWeb.com ] Udemy - Verilog on Intel (Altera) FPGA.zip

[ DevCourseWeb.com ] Udemy - Verilog on Intel (Altera) FPGA.zip 3.1 GB

[磁力链接] 添加时间:2020-12-28 大小:3.1 GB 最近下载:2025-05-12 热度:4102

[压缩文件] [ DevCourseWeb.com ] Udemy - FPGA Design - Glitch in Counters - Analysis using Simulator (updated).zip

[ DevCourseWeb.com ] Udemy - FPGA Design - Glitch in Counters - Analysis using Simulator (updated).zip 2.8 GB

[磁力链接] 添加时间:2021-02-04 大小:2.8 GB 最近下载:2025-05-05 热度:1577

[压缩文件] [ CourseBoat.com ] Udemy - Video Processing with FPGA.zip

[ CourseBoat.com ] Udemy - Video Processing with FPGA.zip 2.8 GB

[磁力链接] 添加时间:2021-04-30 大小:2.8 GB 最近下载:2025-05-12 热度:5500

[影视] [ DevCourseWeb.com ] Udemy - Hands-on development of cpu- soc on FPGA using vhdl(verilog)

~Get Your Files Here !/18 -888.mp4 461.5 MB
~Get Your Files Here !/14 -how to control memory operation, register operation, alu operation etc.mp4 304.8 MB
~Get Your Files Here !/6 -Extracting instruction set from RISC-V datasheet.mp4 261.9 MB
~Get Your Files Here !/8 -how to setup the read and write register alias table.mp4 203.3 MB
~Get Your Files Here !/7 -introducing the counter-track out-of-order execution.mp4 176.0 MB
~Get Your Files Here !/17 -the cache control.mp4 171.0 MB
~Get Your Files Here !/16 -how to setup the cache control for hit, miss, cache address and memory address.mp4 150.4 MB
~Get Your Files Here !/15 -how control handles cache misses and cache hit.mp4 128.1 MB
~Get Your Files Here !/13 -how to connect different units using the control.mp4 127.9 MB
~Get Your Files Here !/19 -top wiring and conclusion.mp4 110.6 MB
~Get Your Files Here !/3 -accessing resource file.mp4 110.4 MB
~Get Your Files Here !/9 -feedback how to return registers after instruction exec using output buffers.mp4 101.4 MB
~Get Your Files Here !/5 -how to link program memory to instruction buffer and program counter buffer.mp4 86.8 MB
~Get Your Files Here !/11 -architecture of a register bank.mp4 72.5 MB
~Get Your Files Here !/12 -how to handle multiple function units. introducing memory buffers.mp4 54.7 MB
~Get Your Files Here !/10 -How to design a simple ALU.mp4 49.2 MB
~Get Your Files Here !/2 -Architecture of the design.mp4 47.9 MB
~Get Your Files Here !/4 -How to design the program memory.mp4 39.5 MB
~Get Your Files Here !/1 -Introduction.mp4 21.2 MB
~Get Your Files Here !/3 -class_resources.zip 11.6 MB

[磁力链接] 添加时间:2025-02-28 大小:2.7 GB 最近下载:2025-05-13 热度:723

[影视] [FreeTutorials.Us] Udemy - Learn VHDL and FPGA Development

16. Lab 6 - Multiplier/2. BASYS 3 Multiplier Demonstration.mp4 107.3 MB
5. VHDL Coding Structure/3. VHDL Design Architecture Styles.mp4 102.2 MB
11. Lab 1 - Full Adder/2. BASYS 3 Full Adder Demonstration.mp4 92.1 MB
8. FPGA Development Boards/2. BASYS 3 Board Overview.mp4 88.5 MB
17. Lab 7 - RC Servo/2. BASYS 3 RC Servo Demonstration.mp4 85.6 MB
4. VHDL Syntax/2. If Statement Case Statement.mp4 79.9 MB
13. Lab 3 - Universal Shift Register/2. BASYS 3 Universal Shift Register Demonstration.mp4 74.1 MB
4. VHDL Syntax/3. For Loop While Loop.mp4 73.8 MB
13. Lab 3 - Universal Shift Register/4. BASYS 2 Universal Shift Register Solution.mp4 73.0 MB
13. Lab 3 - Universal Shift Register/3. BASYS 2 Universal Shift Register Demonstration.mp4 65.3 MB
16. Lab 6 - Multiplier/3. BASYS 2 Multiplier Demonstration.mp4 64.9 MB
5. VHDL Coding Structure/2. VHDL Design Structure.mp4 63.8 MB
4. VHDL Syntax/6. VHDL Processes and Concurrent Statement.mp4 58.4 MB
2. Introduction/2. Introduction to VHDL.mp4 58.0 MB
3. VHDL Data Types/3. Unsigned Signed Data Types.mp4 49.8 MB
12. Lab 2 - Shift Register/2. BASYS 3 Shift Register Demonstration.mp4 49.1 MB
6. Test Bench/1. Test Benches Introduction.mp4 48.6 MB
14. Lab 4 - 7 Segment Display/3. BASYS 2 - 7 Segment Display Demonstration.mp4 47.6 MB
14. Lab 4 - 7 Segment Display/2. BASYS 3 - 7 Segment Display Demonstration.mp4 46.0 MB
3. VHDL Data Types/2. Signals Variables Constants.mp4 43.6 MB

[磁力链接] 添加时间:2020-03-06 大小:2.1 GB 最近下载:2025-05-12 热度:3514

[影视] [FreeTutorials.Us] Udemy - Learn VHDL and FPGA Development

16. Lab 6 - Multiplier/2. BASYS 3 Multiplier Demonstration.mp4 107.3 MB
5. VHDL Coding Structure/3. VHDL Design Architecture Styles.mp4 102.2 MB
11. Lab 1 - Full Adder/2. BASYS 3 Full Adder Demonstration.mp4 92.1 MB
8. FPGA Development Boards/2. BASYS 3 Board Overview.mp4 88.5 MB
17. Lab 7 - RC Servo/2. BASYS 3 RC Servo Demonstration.mp4 85.6 MB
4. VHDL Syntax/2. If Statement Case Statement.mp4 79.9 MB
13. Lab 3 - Universal Shift Register/2. BASYS 3 Universal Shift Register Demonstration.mp4 74.1 MB
4. VHDL Syntax/3. For Loop While Loop.mp4 73.8 MB
13. Lab 3 - Universal Shift Register/4. BASYS 2 Universal Shift Register Solution.mp4 73.0 MB
13. Lab 3 - Universal Shift Register/3. BASYS 2 Universal Shift Register Demonstration.mp4 65.3 MB
16. Lab 6 - Multiplier/3. BASYS 2 Multiplier Demonstration.mp4 64.9 MB
5. VHDL Coding Structure/2. VHDL Design Structure.mp4 63.8 MB
4. VHDL Syntax/6. VHDL Processes and Concurrent Statement.mp4 58.4 MB
2. Introduction/2. Introduction to VHDL.mp4 58.0 MB
3. VHDL Data Types/3. Unsigned Signed Data Types.mp4 49.8 MB
12. Lab 2 - Shift Register/2. BASYS 3 Shift Register Demonstration.mp4 49.1 MB
6. Test Bench/1. Test Benches Introduction.mp4 48.6 MB
14. Lab 4 - 7 Segment Display/3. BASYS 2 - 7 Segment Display Demonstration.mp4 47.6 MB
14. Lab 4 - 7 Segment Display/2. BASYS 3 - 7 Segment Display Demonstration.mp4 46.0 MB
3. VHDL Data Types/2. Signals Variables Constants.mp4 43.6 MB

[磁力链接] 添加时间:2020-03-30 大小:2.1 GB 最近下载:2020-03-30 热度:2

[其他] Learn VHDL, ISE and FPGA by Designing a Basic Home Alarm

LEARN_VHDL_ISE_AND_FPGA_BY_DESIGNING.tgz 2.1 GB
Torrent Downloaded From ExtraTorrent.cc.txt 352 Bytes
Torrent downloaded from demonoid.pw.txt 46 Bytes

[磁力链接] 添加时间:2020-10-26 大小:2.1 GB 最近下载:2025-05-13 热度:5432

[影视] [ DevCourseWeb.com ] Udemy - PYNQ FPGA Development with Python Programming and VIVADO

~Get Your Files Here !/6. Section 6 Creating Custom Overlay (VIVADO Project) for PYNQ/1. Creating Custom Overlay on PYNQ Addition & Multiplication Application.mp4 197.3 MB
~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/3. Section3_2 Python OpenCV Development with PYNQ FPGA Part I OpenCV Basics.mp4 152.3 MB
~Get Your Files Here !/5. Section 5 Machine Learning with Python in PYNQ/1. Machine Learning with Python.mp4 146.8 MB
~Get Your Files Here !/7. Section 7 Creating Custom Python Function Accelerator on PYNQ with VIVADO tool/1. Accelerating Custom Image Processing Function on PYNQ.mp4 145.5 MB
~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/1. Section3_0_Python_Overview.mp4 143.1 MB
~Get Your Files Here !/1. Introduction to PYNQ Architecture/1. PYNQ FPGA Introduction Part I.mp4 130.3 MB
~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/5. Python OpenCV HDMI Streaming & Processing.mp4 129.8 MB
~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/2. Section3_1 Python Programming, Conditional Statements and Loops with PYNQ GPIO.mp4 124.8 MB
~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/4. Section3_2 Python OpenCV Development with PYNQ Part II Face & Eye Detection.mp4 117.7 MB
~Get Your Files Here !/1. Introduction to PYNQ Architecture/3. Section 1 PYNQ Boards & Accessories [Demo].mp4 114.8 MB
~Get Your Files Here !/1. Introduction to PYNQ Architecture/2. PYNQ Introduction Part II.mp4 102.0 MB
~Get Your Files Here !/2. PYNQ Development Methodologies/2. PYNQ FPGA Board Setup & Basic Programming Demo.mp4 101.2 MB
~Get Your Files Here !/2. PYNQ Development Methodologies/1. PYNQ Development Methodologies Overview.mp4 98.9 MB
~Get Your Files Here !/1. Introduction to PYNQ Architecture/4. PYNQ-Z2 Unboxing and Demo [Optional].mp4 97.4 MB
~Get Your Files Here !/6. Section 6 Creating Custom Overlay (VIVADO Project) for PYNQ/3. Creating PYNQ VDMA Overlay with VIVADO 2021.1 and Python-Notebook.mp4 89.4 MB
~Get Your Files Here !/4. Section 4 Installing Python Library in PYNQ/1. Installing Cryptography Python Library on PYNQ.mp4 55.9 MB
~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/6. PYNQ-License Plate Localizer on Python OpenCV.mp4 42.9 MB
~Get Your Files Here !/6. Section 6 Creating Custom Overlay (VIVADO Project) for PYNQ/PYNQ_VDMA_Overlay_Sources_HWH_BIT_IPYNB_JPG_S9_2021/vdma/vdma.bit 4.0 MB
~Get Your Files Here !/7. Section 7 Creating Custom Python Function Accelerator on PYNQ with VIVADO tool/project_resizer/resizer.bit 4.0 MB
~Get Your Files Here !/5. Section 5 Machine Learning with Python in PYNQ/Char_Recognition_with_PYNQ_V2.ipynb 3.7 MB