fpga -磁力猫 -最好用的磁力搜索引擎

[其他] National Instruments LabView v8.6 FPGA Module

TLF-SOFT-NI.LabVIEW.v8.6.FPGA.Module.ISO-TBE-CD2.bin 767.6 MB
TLF-SOFT-NI.LabVIEW.v8.6.FPGA.Module.ISO-TBE-CD1.bin 684.1 MB
TLF-SOFT-NI.LabVIEW.v8.6.FPGA.Module.ISO-TBE.nfo 11.7 kB
TLF-SOFT-NI.LabVIEW.v8.6.FPGA.Module.ISO-TBE-CD1.cue 114 Bytes
TLF-SOFT-NI.LabVIEW.v8.6.FPGA.Module.ISO-TBE-CD2.cue 114 Bytes

[磁力链接] 添加时间:2020-04-21 大小:1.5 GB 最近下载:2025-05-13 热度:3099

[影视] [ DevCourseWeb.com ] Udemy - FPGA (Field-Programmable Gate Array) Design and Implementation

~Get Your Files Here !/03 - FPGA Design Flows & Design Tools/001 FPGA Design Flows & Design Tools.mp4 285.8 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/009 Design Examples.mp4 226.6 MB
~Get Your Files Here !/20 - Memristive FPGA/001 Memristive FPGA.mp4 215.6 MB
~Get Your Files Here !/12 - Reconfigurable Hardware/001 Reconfigurable Hardware.mp4 209.9 MB
~Get Your Files Here !/05 - Simulate and Implement SOPC Design/001 Simulate and Implement SOPC Design.mp4 198.1 MB
~Get Your Files Here !/01 - Introduction to FPGA (Field Programmable Gate Arrays)/001 Introduction to FPGA (Field Programmable Gate Arrays).mp4 192.1 MB
~Get Your Files Here !/21 - Mentor Graphics Tools & Guidelines/001 Mentor Graphics Tools & Guidelines.mp4 184.3 MB
~Get Your Files Here !/09 - Image Processing using FPGA/001 Image Processing using FPGA.mp4 179.7 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/006 Visual Verification of Designs.mp4 165.7 MB
~Get Your Files Here !/19 - Programmable Chips and Boards/001 Programmable Chips and Boards.mp4 163.7 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/008 Finite State Machines - part 2.mp4 153.1 MB
~Get Your Files Here !/14 - FPGA implementation of DSP Circuits/001 FPGA implementation of DSP Circuits.mp4 149.7 MB
~Get Your Files Here !/15 - Reversible Logic Circuits/001 Reversible Logic Circuits.mp4 143.4 MB
~Get Your Files Here !/07 - UART SDRAM Python/001 UART SDRAM Python.mp4 132.5 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/007 Finite State Machines - part 1.mp4 132.3 MB
~Get Your Files Here !/11 - Protoflex/001 Protoflex.mp4 123.6 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/004 Procedural Assignments.mp4 119.6 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/001 Introduction to FPGA Design using Verilog.mp4 115.5 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/002 Verilog overview.mp4 111.3 MB
~Get Your Files Here !/13 - Wordcount using MapReduce for FPGA/001 Wordcount using MapReduce for FPGA.mp4 109.6 MB

[磁力链接] 添加时间:2022-03-03 大小:4.3 GB 最近下载:2025-05-13 热度:7857

[其他] fpga-gnw-opt

Hardware - Frame/Crab Grab (White case).gnw 3.3 MB
Hardware - Frame/Crab Grab.gnw 3.3 MB
Hardware - Frame/Donkey Kong II.gnw 3.3 MB
Hardware - Frame/Donkey Kong Jr. (New Wide Screen).gnw 3.3 MB
Hardware - Frame/Donkey Kong.gnw 3.3 MB
Hardware - Frame/Fire Attack (Bandits).gnw 3.3 MB
Hardware - Frame/Fire Attack.gnw 3.3 MB
Hardware - Frame/Green House.gnw 3.3 MB
Hardware - Frame/Life Boat.gnw 3.3 MB
Hardware - Frame/Manhole (New Wide Screen).gnw 3.3 MB
Hardware - Frame/Mario Bros..gnw 3.3 MB
Hardware - Frame/Mario's Cement Factory (New Wide Screen).gnw 3.3 MB
Hardware - Frame/Mickey & Donald.gnw 3.3 MB
Hardware - Frame/Oil Panic.gnw 3.3 MB
Hardware - Frame/Rain Shower.gnw 3.3 MB
Hardware - Frame/Snoopy Tennis.gnw 3.3 MB
Hardware - Frame/Spitball Sparky (White case).gnw 3.3 MB
Hardware - Frame/Spitball Sparky.gnw 3.3 MB
Hardware - Frame/Squish.gnw 3.3 MB
Hardware - Frame/Tropical Fish.gnw 3.3 MB

[磁力链接] 添加时间:2023-11-07 大小:1.2 GB 最近下载:2025-05-13 热度:4432

[其他] Learn VHDL, ISE and FPGA by Designing a Basic Home Alarm

LEARN_VHDL_ISE_AND_FPGA_BY_DESIGNING.tgz 2.1 GB
Torrent Downloaded From ExtraTorrent.cc.txt 352 Bytes
Torrent downloaded from demonoid.pw.txt 46 Bytes

[磁力链接] 添加时间:2020-10-26 大小:2.1 GB 最近下载:2025-05-13 热度:5432

[影视] [ DevCourseWeb.com ] Udemy - Hands-on development of cpu- soc on FPGA using vhdl(verilog)

~Get Your Files Here !/18 -888.mp4 461.5 MB
~Get Your Files Here !/14 -how to control memory operation, register operation, alu operation etc.mp4 304.8 MB
~Get Your Files Here !/6 -Extracting instruction set from RISC-V datasheet.mp4 261.9 MB
~Get Your Files Here !/8 -how to setup the read and write register alias table.mp4 203.3 MB
~Get Your Files Here !/7 -introducing the counter-track out-of-order execution.mp4 176.0 MB
~Get Your Files Here !/17 -the cache control.mp4 171.0 MB
~Get Your Files Here !/16 -how to setup the cache control for hit, miss, cache address and memory address.mp4 150.4 MB
~Get Your Files Here !/15 -how control handles cache misses and cache hit.mp4 128.1 MB
~Get Your Files Here !/13 -how to connect different units using the control.mp4 127.9 MB
~Get Your Files Here !/19 -top wiring and conclusion.mp4 110.6 MB
~Get Your Files Here !/3 -accessing resource file.mp4 110.4 MB
~Get Your Files Here !/9 -feedback how to return registers after instruction exec using output buffers.mp4 101.4 MB
~Get Your Files Here !/5 -how to link program memory to instruction buffer and program counter buffer.mp4 86.8 MB
~Get Your Files Here !/11 -architecture of a register bank.mp4 72.5 MB
~Get Your Files Here !/12 -how to handle multiple function units. introducing memory buffers.mp4 54.7 MB
~Get Your Files Here !/10 -How to design a simple ALU.mp4 49.2 MB
~Get Your Files Here !/2 -Architecture of the design.mp4 47.9 MB
~Get Your Files Here !/4 -How to design the program memory.mp4 39.5 MB
~Get Your Files Here !/1 -Introduction.mp4 21.2 MB
~Get Your Files Here !/3 -class_resources.zip 11.6 MB

[磁力链接] 添加时间:2025-02-28 大小:2.7 GB 最近下载:2025-05-13 热度:723

[压缩文件] [ FreeCourseWeb.com ] Udemy - Learn VHDL Design using Xilinx Zynq-7000 ARM-FPGA SoC.zip

[ FreeCourseWeb.com ] Udemy - Learn VHDL Design using Xilinx Zynq-7000 ARM-FPGA SoC.zip 1.6 GB

[磁力链接] 添加时间:2020-04-14 大小:1.6 GB 最近下载:2025-05-13 热度:6858

[影视] FPGA Filter

2 - FPGA Median Filter/7 - FPGA Median Filter 04 Median Module Coding.mp4 95.6 MB
1 - FPGA Mean Average Filter/3 - FPGA Mean Average Filter 03 Simulation.mp4 71.7 MB
2 - FPGA Median Filter/8 - FPGA Median Filter 05 Median Module Simulation.mp4 67.3 MB
3 - FPGA Gaussian Filter/11 - FPGA Gaussian Filter 03 Simulation.mp4 67.1 MB
3 - FPGA Gaussian Filter/10 - FPGA Gaussian Filter 02 Coding.mp4 63.5 MB
2 - FPGA Median Filter/6 - FPGA Median Filter 03 Sort Module Simulation.mp4 63.1 MB
1 - FPGA Mean Average Filter/2 - FPGA Mean Average Filter 02 Coding.mp4 52.8 MB
2 - FPGA Median Filter/5 - FPGA Median Filter 02 Sort Module Coding.mp4 47.8 MB
3 - FPGA Gaussian Filter/9 - FPGA Gaussian Filter 01 Introduction.mp4 32.3 MB
2 - FPGA Median Filter/4 - FPGA Median Filter 01 Introduction.mp4 17.4 MB
1 - FPGA Mean Average Filter/1 - FPGA Mean Average Filter 01 Introduction.mp4 11.5 MB
2 - FPGA Median Filter/7 - FPGA Median Filter 04 English.vtt 13.4 kB
3 - FPGA Gaussian Filter/10 - FPGA Gaussian Filter 02 English.vtt 9.3 kB
2 - FPGA Median Filter/8 - FPGA Median Filter 05 English.vtt 7.7 kB
1 - FPGA Mean Average Filter/3 - FPGA Mean Average Filter 03 English.vtt 7.4 kB
1 - FPGA Mean Average Filter/2 - FPGA Mean Average Filter 02 English.vtt 7.2 kB
2 - FPGA Median Filter/6 - FPGA Median Filter 03 English.vtt 7.0 kB
3 - FPGA Gaussian Filter/11 - FPGA Gaussian Filter 03 English.vtt 6.8 kB
2 - FPGA Median Filter/5 - FPGA Median Filter 02 English.vtt 6.5 kB
3 - FPGA Gaussian Filter/9 - FPGA Gaussian Filter 01 English.vtt 6.3 kB

[磁力链接] 添加时间:2023-07-14 大小:590.2 MB 最近下载:2025-05-13 热度:4254

[影视] [udemy] Xilinx Vivado Beginners Course to FPGA Development in VHDL [MyFOM]

Section 2 Lab 1/Implementation of VHDL Design in Vivado and IO Pin Planning.mp4 72.5 MB
Section 4 Lab 3/Designing a Microblaze Soft Processor in Vivado IP Integrator.mp4 62.0 MB
Section 4 Lab 3/Learn VHDL by Example.mp4 60.0 MB
Section 3 Lab 2/Design a Block RAM in IP Integrator.mp4 53.0 MB
Section 2 Lab 1/Downloading the Bit-stream to the FPGA.mp4 48.5 MB
Section 2 Lab 1/Introduction to the Vivado Design Suite Interface and Creating a New Project.mp4 47.8 MB
Section 1 Introduction to Vivado/How to Download and Install Xilinx Vivado Design Suite.mp4 42.2 MB
Section 2 Lab 1/Coding and Simulating Simple VHDL in Vivado.mp4 36.2 MB
Section 3 Lab 2/Simulating BRAM memory IP in Vivado.mp4 23.3 MB
Section 4 Lab 3/Generating a Microblaze using TCL commands in Vivado.mp4 21.1 MB
Section 1 Introduction to Vivado/Introduction.mp4 16.9 MB
MyFreeOnlineMovies.co.uk.html 189.0 kB
Torrent Downloaded from Glodls.to.txt 237 Bytes
Section 4 Lab 3/New Text Document.txt 52 Bytes
Section 5 Conclusion and Bonus Section/Sorry the files are deleted bare with me.txt 51 Bytes

[磁力链接] 添加时间:2020-02-28 大小:483.8 MB 最近下载:2025-05-13 热度:6376

[影视] [ DevCourseWeb.com ] Udemy - Digital IC - FPGA Design P3 - Common Used Hardware Architectures

~Get Your Files Here !/2 - SRAM/1 -Behavior of SRAM and Usage Suggestions.mp4 403.5 MB
~Get Your Files Here !/4 - Pipeline Design/2 -Pipeline Design Example BIN2BCD.mp4 315.3 MB
~Get Your Files Here !/3 - Handshake Interface and Synchronous FIFO/1 -Handshake Interface and Sync_FIFO.mp4 208.8 MB
~Get Your Files Here !/4 - Pipeline Design/1 -Pipeline Fundamental.mp4 132.6 MB
~Get Your Files Here !/3 - Handshake Interface and Synchronous FIFO/2 -Depth Calculation for FIFO.mp4 109.2 MB
~Get Your Files Here !/1 - Introduction/1 -Introduction.mp4 14.9 MB
~Get Your Files Here !/Bonus Resources.txt 386 Bytes
Get Bonus Downloads Here.url 182 Bytes

[磁力链接] 添加时间:2025-01-13 大小:1.2 GB 最近下载:2025-05-13 热度:600

[影视] FPGA Development in VHDL - Beyond the Basics

03.Working with Custom Data Types/08.Demo.mp4 84.1 MB
06.Constructing State Machines/05.Demo - Combination Lock (Mealy).mp4 62.8 MB
05.Keeping Code Organized with Subprograms and Packages/05.Generics.mp4 50.4 MB
05.Keeping Code Organized with Subprograms and Packages/06.Resolution Functions.mp4 42.9 MB
06.Constructing State Machines/04.Demo - Traffic Lights (Moore).mp4 41.5 MB
07.Testing Your Designs/04.Testing with VUnit.mp4 30.8 MB
02.Developing for the FPGA/05.Demo - Compilation Report.mp4 26.8 MB
07.Testing Your Designs/03.A Sample Testbench.mp4 26.7 MB
02.Developing for the FPGA/07.Demo - MATLAB HDL Coder.mp4 23.5 MB
04.Monitoring Signal States with Attributes/04.Function Kind Attributes.mp4 15.8 MB
06.Constructing State Machines/06.State Encoding Styles.mp4 13.9 MB
05.Keeping Code Organized with Subprograms and Packages/03.Procedures.mp4 10.9 MB
03.Working with Custom Data Types/03.Arrays and Ranges.mp4 10.8 MB
07.Testing Your Designs/02.Testing and Testbenches.mp4 8.1 MB
04.Monitoring Signal States with Attributes/03.Value Kind Attributes.mp4 7.5 MB
03.Working with Custom Data Types/02.Standard Data Types Recap.mp4 6.5 MB
02.Developing for the FPGA/04.Compilation Process.mp4 5.6 MB
05.Keeping Code Organized with Subprograms and Packages/04.Constants.mp4 5.0 MB
04.Monitoring Signal States with Attributes/07.User-defined Attributes.mp4 4.5 MB
05.Keeping Code Organized with Subprograms and Packages/02.Design Unit Recap.mp4 4.4 MB

[磁力链接] 添加时间:2020-02-14 大小:541.2 MB 最近下载:2025-05-13 热度:14074

[文档书籍] HDL Books - VHDL FPGA CPLD Verilog Digital Electronics eBook

0131972553 - (2005) Digital Fundamentals.pdf 492.0 MB
0126912955 - (2000) Engineering Digital Design.pdf 50.6 MB
0792397460 - (1996) LOGIC SYNTHESIS AND VERIFICATION ALGORITHMS.pdf 41.7 MB
0965193438 - (1996) HDL Chip Design- A Practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs Using VHDL or Verilog.pdf 40.6 MB
0471720925 - (2006) RTL Hardware Design Using VHDL Coding for Efficiency, Portability, and Scalability.pdf 35.8 MB
0072460857 - (2005) Fundamentals of Digital Logic with VHDL Design.pdf 35.6 MB
0132543036 - (2011) Digital Electronics - A Practical Approach with VHDL - 9th Edition.pdf 33.6 MB
0470828498 - (2011) Design for Embedded Image Processing on FPGAs.pdf 28.7 MB
0070471649 - (1999) Verilog Digital System Design.pdf 28.3 MB
0134516753 - (1996) Verilog HDL A Guide to Digital Design and Synthesis B.pdf 22.4 MB
0470185317 - (2008) FPGA Prototyping by VHDL Examples - Xilinx Spartan-3 Version.pdf 22.3 MB
0131543180 - (2005) Practical FPGA Programming in C.chm 18.2 MB
1402055293 - (2007) Processor Design System-On-Chip Computing for ASICs and FPGAs.pdf 15.6 MB
0387284850 - (2006) FPGA Implementations of neural networks.pdf 14.7 MB
0136507638 - (1996) VHDL Made Easy.pdf 13.8 MB
0412616505 - (1997) VHDL A logic synthesis approach.pdf 13.4 MB
1934404055 - (2007) Digital Circuit Analysis and Design with Simulink Modeling and Introduction to CPLDs and FPGAs 2nd Ed.pdf 13.4 MB
0077221435 - (2008) Fundamentals of Digital Logic with VHDL Design - Ed. 3.pdf 12.8 MB
0792395980 - (1995) VHDL Coding Styles and Methodologies.pdf 12.7 MB
0123744385 - (2009) Low-Power Design of Nanometer FPGAs Architecture and EDA.pdf 12.6 MB

[磁力链接] 添加时间:2020-02-03 大小:1.2 GB 最近下载:2025-05-13 热度:14366

[压缩文件] [ FreeCourseWeb.com ] Udemy - FPGA Drive 7 Segment Display.zip

[ FreeCourseWeb.com ] Udemy - FPGA Drive 7 Segment Display.zip 1.2 GB

[磁力链接] 添加时间:2021-02-03 大小:1.2 GB 最近下载:2025-05-13 热度:4384

[其他] fpga-gnw-opt

Hardware - Frame/Crab Grab (White case).gnw 3.3 MB
Hardware - Frame/Crab Grab.gnw 3.3 MB
Hardware - Frame/Donkey Kong II.gnw 3.3 MB
Hardware - Frame/Donkey Kong Jr. (New Wide Screen).gnw 3.3 MB
Hardware - Frame/Donkey Kong.gnw 3.3 MB
Hardware - Frame/Fire Attack (Bandits).gnw 3.3 MB
Hardware - Frame/Fire Attack.gnw 3.3 MB
Hardware - Frame/Green House.gnw 3.3 MB
Hardware - Frame/Life Boat.gnw 3.3 MB
Hardware - Frame/Manhole (New Wide Screen).gnw 3.3 MB
Hardware - Frame/Mario Bros..gnw 3.3 MB
Hardware - Frame/Mario's Cement Factory (New Wide Screen).gnw 3.3 MB
Hardware - Frame/Mickey & Donald.gnw 3.3 MB
Hardware - Frame/Oil Panic.gnw 3.3 MB
Hardware - Frame/Rain Shower.gnw 3.3 MB
Hardware - Frame/Snoopy Tennis.gnw 3.3 MB
Hardware - Frame/Spitball Sparky (White case).gnw 3.3 MB
Hardware - Frame/Spitball Sparky.gnw 3.3 MB
Hardware - Frame/Squish.gnw 3.3 MB
Hardware - Frame/Tropical Fish.gnw 3.3 MB

[磁力链接] 添加时间:2024-01-26 大小:1.6 GB 最近下载:2025-05-13 热度:1885

[压缩文件] neo-geo-1g1r-darksoft-converted-to-neosd-mister-fpga

NEOGEO.zip 1.8 GB
neo-geo-1g1r-darksoft-converted-to-neosd-mister-fpga_meta.sqlite 28.7 kB
neo-geo-1g1r-darksoft-converted-to-neosd-mister-fpga_meta.xml 3.7 kB

[磁力链接] 添加时间:2023-08-31 大小:1.8 GB 最近下载:2025-05-13 热度:2374

[压缩文件] [ DevCourseWeb.com ] Udemy - FPGA Embedded Design, Part 3 - EDA Tools.zip

[ DevCourseWeb.com ] Udemy - FPGA Embedded Design, Part 3 - EDA Tools.zip 1.2 GB

[磁力链接] 添加时间:2021-07-18 大小:1.2 GB 最近下载:2025-05-13 热度:4277

[影视] [ CourseLala.com ] Udemy - FPGA Piano

~Get Your Files Here !/8. One Key Module Coding.mp4 190.6 MB
~Get Your Files Here !/2. Make Buzzer Buzzing.mp4 184.6 MB
~Get Your Files Here !/9. One Key Module Simulation.mp4 128.6 MB
~Get Your Files Here !/6. Buzzer Module Simulation.mp4 108.1 MB
~Get Your Files Here !/5. Buzzer Module Coding.mp4 101.6 MB
~Get Your Files Here !/12. Key Module Solution2 Coding.mp4 88.4 MB
~Get Your Files Here !/11. Key Module Solution1 Simultion.mp4 87.2 MB
~Get Your Files Here !/10. Key Module Solution1 Coding.mp4 74.9 MB
~Get Your Files Here !/16. LED Module Simulation.mp4 71.6 MB
~Get Your Files Here !/19. Run on Board.mp4 66.7 MB
~Get Your Files Here !/18. Top Module Simulation.mp4 66.7 MB
~Get Your Files Here !/17. Top Module Coding.mp4 59.1 MB
~Get Your Files Here !/1. System Target.mp4 57.9 MB
~Get Your Files Here !/15. LED Module Coding.mp4 48.3 MB
~Get Your Files Here !/7. Key Module Status Machine.mp4 33.3 MB
~Get Your Files Here !/13. Key Module Solution2 Simulation.mp4 23.1 MB
~Get Your Files Here !/4. Buzzer Module Status Machine.mp4 18.1 MB
~Get Your Files Here !/3. System Analysis.mp4 15.4 MB
~Get Your Files Here !/14. LED Module Status Machine.mp4 10.1 MB
~Get Your Files Here !/8. One Key Module Coding.srt 31.9 kB

[磁力链接] 添加时间:2022-06-22 大小:1.4 GB 最近下载:2025-05-13 热度:2983

[影视] [ DevCourseWeb.com ] Udemy - High-Level Synthesis For Fpga, Part 3 - Advanced

~Get Your Files Here !/6 - Pointers/35 - MultiAccess Pointers on the Interface.mp4 260.9 MB
~Get Your Files Here !/9 - HLS Stream Library/55 - Stream on the Interface.mp4 194.9 MB
~Get Your Files Here !/9 - HLS Stream Library/56 - BlockingNonBlocking.mp4 185.4 MB
~Get Your Files Here !/2 - LAB Setup/5 - Linux Installation.mp4 180.1 MB
~Get Your Files Here !/7 - AXI in HLS/44 - The maxi interface.mp4 161.8 MB
~Get Your Files Here !/3 - MultiCycle Design/14 - BlockLevel Handshake.mp4 154.1 MB
~Get Your Files Here !/6 - Pointers/34 - Pointer Arithmetic.mp4 132.5 MB
~Get Your Files Here !/6 - Pointers/31 - Definition.mp4 128.2 MB
~Get Your Files Here !/7 - AXI in HLS/40 - Memory Mapped Output 01.mp4 127.5 MB
~Get Your Files Here !/3 - MultiCycle Design/9 - Example.mp4 125.2 MB
~Get Your Files Here !/3 - MultiCycle Design/12 - Example with ack.mp4 125.0 MB
~Get Your Files Here !/4 - Streaming/21 - Streaming Example Vivado.mp4 121.5 MB
~Get Your Files Here !/7 - AXI in HLS/43 - Memory Mapped IO.mp4 116.3 MB
~Get Your Files Here !/3 - MultiCycle Design/11 - Example with vld.mp4 112.4 MB
~Get Your Files Here !/6 - Pointers/33 - Pointers on the Interface.mp4 111.2 MB
~Get Your Files Here !/8 - Loops In HLS/48 - Loop Unrolling.mp4 110.3 MB
~Get Your Files Here !/5 - ArrayInHLS/28 - Array ReadWrite Vivado.mp4 110.0 MB
~Get Your Files Here !/7 - AXI in HLS/42 - Memory Mapped Output 02.mp4 100.3 MB
~Get Your Files Here !/6 - Pointers/32 - Native Pointer Casting.mp4 95.1 MB
~Get Your Files Here !/5 - ArrayInHLS/25 - Array Issues.mp4 92.1 MB

[磁力链接] 添加时间:2023-05-12 大小:4.0 GB 最近下载:2025-05-13 热度:3263

[压缩文件] [ FreeCourseWeb.com ] Udemy - FPGA Embedded Design, Part 2 - Basic FPGA Training.zip

[ FreeCourseWeb.com ] Udemy - FPGA Embedded Design, Part 2 - Basic FPGA Training.zip 1.4 GB

[磁力链接] 添加时间:2021-06-02 大小:1.4 GB 最近下载:2025-05-12 热度:6581

[影视] [ DevCourseWeb.com ] Udemy - PYNQ FPGA Development with Python Programming and VIVADO

~Get Your Files Here !/6. Section 6 Creating Custom Overlay (VIVADO Project) for PYNQ/1. Creating Custom Overlay on PYNQ Addition & Multiplication Application.mp4 197.3 MB
~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/3. Section3_2 Python OpenCV Development with PYNQ FPGA Part I OpenCV Basics.mp4 152.3 MB
~Get Your Files Here !/5. Section 5 Machine Learning with Python in PYNQ/1. Machine Learning with Python.mp4 146.8 MB
~Get Your Files Here !/7. Section 7 Creating Custom Python Function Accelerator on PYNQ with VIVADO tool/1. Accelerating Custom Image Processing Function on PYNQ.mp4 145.5 MB
~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/1. Section3_0_Python_Overview.mp4 143.1 MB
~Get Your Files Here !/1. Introduction to PYNQ Architecture/1. PYNQ FPGA Introduction Part I.mp4 130.3 MB
~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/5. Python OpenCV HDMI Streaming & Processing.mp4 129.8 MB
~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/2. Section3_1 Python Programming, Conditional Statements and Loops with PYNQ GPIO.mp4 124.8 MB
~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/4. Section3_2 Python OpenCV Development with PYNQ Part II Face & Eye Detection.mp4 117.7 MB
~Get Your Files Here !/1. Introduction to PYNQ Architecture/3. Section 1 PYNQ Boards & Accessories [Demo].mp4 114.8 MB
~Get Your Files Here !/1. Introduction to PYNQ Architecture/2. PYNQ Introduction Part II.mp4 102.0 MB
~Get Your Files Here !/2. PYNQ Development Methodologies/2. PYNQ FPGA Board Setup & Basic Programming Demo.mp4 101.2 MB
~Get Your Files Here !/2. PYNQ Development Methodologies/1. PYNQ Development Methodologies Overview.mp4 98.9 MB
~Get Your Files Here !/1. Introduction to PYNQ Architecture/4. PYNQ-Z2 Unboxing and Demo [Optional].mp4 97.4 MB
~Get Your Files Here !/6. Section 6 Creating Custom Overlay (VIVADO Project) for PYNQ/3. Creating PYNQ VDMA Overlay with VIVADO 2021.1 and Python-Notebook.mp4 89.4 MB
~Get Your Files Here !/4. Section 4 Installing Python Library in PYNQ/1. Installing Cryptography Python Library on PYNQ.mp4 55.9 MB
~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/6. PYNQ-License Plate Localizer on Python OpenCV.mp4 42.9 MB
~Get Your Files Here !/6. Section 6 Creating Custom Overlay (VIVADO Project) for PYNQ/PYNQ_VDMA_Overlay_Sources_HWH_BIT_IPYNB_JPG_S9_2021/vdma/vdma.bit 4.0 MB
~Get Your Files Here !/7. Section 7 Creating Custom Python Function Accelerator on PYNQ with VIVADO tool/project_resizer/resizer.bit 4.0 MB
~Get Your Files Here !/5. Section 5 Machine Learning with Python in PYNQ/Char_Recognition_with_PYNQ_V2.ipynb 3.7 MB

[磁力链接] 添加时间:2023-08-20 大小:2.0 GB 最近下载:2025-05-12 热度:5154

[影视] [FreeTutorials.Us] Udemy - Learn VHDL and FPGA Development

16. Lab 6 - Multiplier/2. BASYS 3 Multiplier Demonstration.mp4 107.3 MB
5. VHDL Coding Structure/3. VHDL Design Architecture Styles.mp4 102.2 MB
11. Lab 1 - Full Adder/2. BASYS 3 Full Adder Demonstration.mp4 92.1 MB
8. FPGA Development Boards/2. BASYS 3 Board Overview.mp4 88.5 MB
17. Lab 7 - RC Servo/2. BASYS 3 RC Servo Demonstration.mp4 85.6 MB
4. VHDL Syntax/2. If Statement Case Statement.mp4 79.9 MB
13. Lab 3 - Universal Shift Register/2. BASYS 3 Universal Shift Register Demonstration.mp4 74.1 MB
4. VHDL Syntax/3. For Loop While Loop.mp4 73.8 MB
13. Lab 3 - Universal Shift Register/4. BASYS 2 Universal Shift Register Solution.mp4 73.0 MB
13. Lab 3 - Universal Shift Register/3. BASYS 2 Universal Shift Register Demonstration.mp4 65.3 MB
16. Lab 6 - Multiplier/3. BASYS 2 Multiplier Demonstration.mp4 64.9 MB
5. VHDL Coding Structure/2. VHDL Design Structure.mp4 63.8 MB
4. VHDL Syntax/6. VHDL Processes and Concurrent Statement.mp4 58.4 MB
2. Introduction/2. Introduction to VHDL.mp4 58.0 MB
3. VHDL Data Types/3. Unsigned Signed Data Types.mp4 49.8 MB
12. Lab 2 - Shift Register/2. BASYS 3 Shift Register Demonstration.mp4 49.1 MB
6. Test Bench/1. Test Benches Introduction.mp4 48.6 MB
14. Lab 4 - 7 Segment Display/3. BASYS 2 - 7 Segment Display Demonstration.mp4 47.6 MB
14. Lab 4 - 7 Segment Display/2. BASYS 3 - 7 Segment Display Demonstration.mp4 46.0 MB
3. VHDL Data Types/2. Signals Variables Constants.mp4 43.6 MB

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