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[影视]
FPGA Development in VHDL - Beyond the Basics
03.Working with Custom Data Types/08.Demo.mp4
84.1 MB
06.Constructing State Machines/05.Demo - Combination Lock (Mealy).mp4
62.8 MB
05.Keeping Code Organized with Subprograms and Packages/05.Generics.mp4
50.4 MB
05.Keeping Code Organized with Subprograms and Packages/06.Resolution Functions.mp4
42.9 MB
06.Constructing State Machines/04.Demo - Traffic Lights (Moore).mp4
41.5 MB
07.Testing Your Designs/04.Testing with VUnit.mp4
30.8 MB
02.Developing for the FPGA/05.Demo - Compilation Report.mp4
26.8 MB
07.Testing Your Designs/03.A Sample Testbench.mp4
26.7 MB
02.Developing for the FPGA/07.Demo - MATLAB HDL Coder.mp4
23.5 MB
04.Monitoring Signal States with Attributes/04.Function Kind Attributes.mp4
15.8 MB
06.Constructing State Machines/06.State Encoding Styles.mp4
13.9 MB
05.Keeping Code Organized with Subprograms and Packages/03.Procedures.mp4
10.9 MB
03.Working with Custom Data Types/03.Arrays and Ranges.mp4
10.8 MB
07.Testing Your Designs/02.Testing and Testbenches.mp4
8.1 MB
04.Monitoring Signal States with Attributes/03.Value Kind Attributes.mp4
7.5 MB
03.Working with Custom Data Types/02.Standard Data Types Recap.mp4
6.5 MB
02.Developing for the FPGA/04.Compilation Process.mp4
5.6 MB
05.Keeping Code Organized with Subprograms and Packages/04.Constants.mp4
5.0 MB
04.Monitoring Signal States with Attributes/07.User-defined Attributes.mp4
4.5 MB
05.Keeping Code Organized with Subprograms and Packages/02.Design Unit Recap.mp4
4.4 MB
[磁力链接]
添加时间:
2020-02-14
大小:
541.2 MB
最近下载:
2025-05-13
热度:
14074
[影视]
Getting Started with FPGA Programming with VHDL
07.Packages and Components/06.Demo - Packages and Components.mp4
48.3 MB
08.Debugging and Analysis/02.Simulation with ModelSim.mp4
43.4 MB
02.FPGA Technology Overview/04.A Look at the Development Board.mp4
39.9 MB
06.Writing Concurrent Code/07.Demo - Resettable Timer.mp4
39.2 MB
04.Introduction to VHDL/06.Interacting with Board IO.mp4
31.9 MB
05.Writing Sequential Code/08.Demo - Sequential Constructs.mp4
31.5 MB
02.FPGA Technology Overview/05.Setting up the EDA.mp4
20.5 MB
08.Debugging and Analysis/03.SignalTap Logic Analyzer.mp4
19.8 MB
02.FPGA Technology Overview/03.What Is an FPGA.mp4
16.9 MB
04.Introduction to VHDL/04.Ports and Board IO.mp4
15.5 MB
02.FPGA Technology Overview/06.Project Setup.mp4
13.2 MB
02.FPGA Technology Overview/08.Programming the FPGA.mp4
10.9 MB
02.FPGA Technology Overview/07.Pin Assignments and the Pin Planner.mp4
9.8 MB
01.Course Overview/01.Course Overview.mp4
9.2 MB
07.Packages and Components/02.The IEEE Library and Standard Logic.mp4
8.0 MB
03.Digital Design Primer/04.Addition and Multiplication.mp4
8.0 MB
05.Writing Sequential Code/05.More Data Types.mp4
7.3 MB
07.Packages and Components/04.Components and Port Maps.mp4
7.3 MB
03.Digital Design Primer/05.Flip-flop, MUX, and LUT.mp4
7.0 MB
03.Digital Design Primer/03.Logic Gates.mp4
7.0 MB
[磁力链接]
添加时间:
2020-02-27
大小:
520.8 MB
最近下载:
2025-05-12
热度:
19699
[影视]
[udemy] Xilinx Vivado Beginners Course to FPGA Development in VHDL [MyFOM]
Section 2 Lab 1/Implementation of VHDL Design in Vivado and IO Pin Planning.mp4
72.5 MB
Section 4 Lab 3/Designing a Microblaze Soft Processor in Vivado IP Integrator.mp4
62.0 MB
Section 4 Lab 3/Learn VHDL by Example.mp4
60.0 MB
Section 3 Lab 2/Design a Block RAM in IP Integrator.mp4
53.0 MB
Section 2 Lab 1/Downloading the Bit-stream to the FPGA.mp4
48.5 MB
Section 2 Lab 1/Introduction to the Vivado Design Suite Interface and Creating a New Project.mp4
47.8 MB
Section 1 Introduction to Vivado/How to Download and Install Xilinx Vivado Design Suite.mp4
42.2 MB
Section 2 Lab 1/Coding and Simulating Simple VHDL in Vivado.mp4
36.2 MB
Section 3 Lab 2/Simulating BRAM memory IP in Vivado.mp4
23.3 MB
Section 4 Lab 3/Generating a Microblaze using TCL commands in Vivado.mp4
21.1 MB
Section 1 Introduction to Vivado/Introduction.mp4
16.9 MB
MyFreeOnlineMovies.co.uk.html
189.0 kB
Torrent Downloaded from Glodls.to.txt
237 Bytes
Section 4 Lab 3/New Text Document.txt
52 Bytes
Section 5 Conclusion and Bonus Section/Sorry the files are deleted bare with me.txt
51 Bytes
[磁力链接]
添加时间:
2020-02-28
大小:
483.8 MB
最近下载:
2025-05-13
热度:
6376
[影视]
[FreeTutorials.Us] Udemy - Learn VHDL and FPGA Development
16. Lab 6 - Multiplier/2. BASYS 3 Multiplier Demonstration.mp4
107.3 MB
5. VHDL Coding Structure/3. VHDL Design Architecture Styles.mp4
102.2 MB
11. Lab 1 - Full Adder/2. BASYS 3 Full Adder Demonstration.mp4
92.1 MB
8. FPGA Development Boards/2. BASYS 3 Board Overview.mp4
88.5 MB
17. Lab 7 - RC Servo/2. BASYS 3 RC Servo Demonstration.mp4
85.6 MB
4. VHDL Syntax/2. If Statement Case Statement.mp4
79.9 MB
13. Lab 3 - Universal Shift Register/2. BASYS 3 Universal Shift Register Demonstration.mp4
74.1 MB
4. VHDL Syntax/3. For Loop While Loop.mp4
73.8 MB
13. Lab 3 - Universal Shift Register/4. BASYS 2 Universal Shift Register Solution.mp4
73.0 MB
13. Lab 3 - Universal Shift Register/3. BASYS 2 Universal Shift Register Demonstration.mp4
65.3 MB
16. Lab 6 - Multiplier/3. BASYS 2 Multiplier Demonstration.mp4
64.9 MB
5. VHDL Coding Structure/2. VHDL Design Structure.mp4
63.8 MB
4. VHDL Syntax/6. VHDL Processes and Concurrent Statement.mp4
58.4 MB
2. Introduction/2. Introduction to VHDL.mp4
58.0 MB
3. VHDL Data Types/3. Unsigned Signed Data Types.mp4
49.8 MB
12. Lab 2 - Shift Register/2. BASYS 3 Shift Register Demonstration.mp4
49.1 MB
6. Test Bench/1. Test Benches Introduction.mp4
48.6 MB
14. Lab 4 - 7 Segment Display/3. BASYS 2 - 7 Segment Display Demonstration.mp4
47.6 MB
14. Lab 4 - 7 Segment Display/2. BASYS 3 - 7 Segment Display Demonstration.mp4
46.0 MB
3. VHDL Data Types/2. Signals Variables Constants.mp4
43.6 MB
[磁力链接]
添加时间:
2020-03-06
大小:
2.1 GB
最近下载:
2025-05-12
热度:
3514
[影视]
[UdemyCourseDownloader] Learning FPGA Development
5 - 4._Implementation/27. Xilinx_hardware_demo.mp4
22.6 MB
5 - 4._Implementation/26. Xilinx_implementation_demo.mp4
22.0 MB
5 - 4._Implementation/23. Intel_implementation_demo.mp4
13.9 MB
4 - 3._Hardware_Description_Languages/19. 4-bit_adder_simulation_example.mp4
13.1 MB
4 - 3._Hardware_Description_Languages/20. Sequential_logic_simulation_example.mp4
12.3 MB
5 - 4._Implementation/24. Intel_hardware_demo.mp4
12.3 MB
3 - 2._Embedded_Development_Process/09. FPGA_development_process_overview.mp4
9.8 MB
1 - Introduction/01. Get_your_digital_design_journey_started.mp4
9.0 MB
4 - 3._Hardware_Description_Languages/16. Verilog_primer.mp4
8.8 MB
3 - 2._Embedded_Development_Process/10. FPGA_families_and_development_boards.mp4
8.2 MB
2 - 1._Field_Programmable_Gate_Arrays/08. Other_blocks.mp4
7.8 MB
2 - 1._Field_Programmable_Gate_Arrays/06. Inside_an_FPGA_-_Logic_blocks.mp4
7.6 MB
4 - 3._Hardware_Description_Languages/15. Verilog_and_VHDL.mp4
7.1 MB
4 - 3._Hardware_Description_Languages/14. Digital_system_modeling.mp4
6.6 MB
Ex_Files_FPGA_Development.zip
5.6 MB
5 - 4._Implementation/25. Demo_system_for_the_Xilinx_platform.mp4
5.0 MB
5 - 4._Implementation/22. Demo_system_for_the_Intel_platform.mp4
4.4 MB
3 - 2._Embedded_Development_Process/11. Electronic_design_automation_tools.mp4
3.8 MB
2 - 1._Field_Programmable_Gate_Arrays/07. Inside_an_FPGA_-_Interconnects.mp4
3.4 MB
5 - 4._Implementation/21. FPGA_example_implementation_requirements.mp4
3.2 MB
[磁力链接]
添加时间:
2020-03-19
大小:
207.4 MB
最近下载:
2025-05-12
热度:
2341
[影视]
[FreeTutorials.Us] Udemy - Learn VHDL and FPGA Development
16. Lab 6 - Multiplier/2. BASYS 3 Multiplier Demonstration.mp4
107.3 MB
5. VHDL Coding Structure/3. VHDL Design Architecture Styles.mp4
102.2 MB
11. Lab 1 - Full Adder/2. BASYS 3 Full Adder Demonstration.mp4
92.1 MB
8. FPGA Development Boards/2. BASYS 3 Board Overview.mp4
88.5 MB
17. Lab 7 - RC Servo/2. BASYS 3 RC Servo Demonstration.mp4
85.6 MB
4. VHDL Syntax/2. If Statement Case Statement.mp4
79.9 MB
13. Lab 3 - Universal Shift Register/2. BASYS 3 Universal Shift Register Demonstration.mp4
74.1 MB
4. VHDL Syntax/3. For Loop While Loop.mp4
73.8 MB
13. Lab 3 - Universal Shift Register/4. BASYS 2 Universal Shift Register Solution.mp4
73.0 MB
13. Lab 3 - Universal Shift Register/3. BASYS 2 Universal Shift Register Demonstration.mp4
65.3 MB
16. Lab 6 - Multiplier/3. BASYS 2 Multiplier Demonstration.mp4
64.9 MB
5. VHDL Coding Structure/2. VHDL Design Structure.mp4
63.8 MB
4. VHDL Syntax/6. VHDL Processes and Concurrent Statement.mp4
58.4 MB
2. Introduction/2. Introduction to VHDL.mp4
58.0 MB
3. VHDL Data Types/3. Unsigned Signed Data Types.mp4
49.8 MB
12. Lab 2 - Shift Register/2. BASYS 3 Shift Register Demonstration.mp4
49.1 MB
6. Test Bench/1. Test Benches Introduction.mp4
48.6 MB
14. Lab 4 - 7 Segment Display/3. BASYS 2 - 7 Segment Display Demonstration.mp4
47.6 MB
14. Lab 4 - 7 Segment Display/2. BASYS 3 - 7 Segment Display Demonstration.mp4
46.0 MB
3. VHDL Data Types/2. Signals Variables Constants.mp4
43.6 MB
[磁力链接]
添加时间:
2020-03-30
大小:
2.1 GB
最近下载:
2020-03-30
热度:
2
[影视]
[ FreeCourseWeb.com ] Udemy - FPGA Design with MATLAB & Simulink
~Get Your Files Here !/4. Section_4 Advance Design with HDL Coder/1. Section 4 Advance Design with HDL Coder Overview.mp4
162.5 MB
~Get Your Files Here !/3. Section_3 Project with System Generator/2. Section 3 Lab 30 Basic Project with System Generator.mp4
122.9 MB
~Get Your Files Here !/1. Section_1 Installation of MatlabSimulink and VIVADOISE/1. Installation of MatlabSimulink and VIVADOISE.mp4
74.3 MB
~Get Your Files Here !/6. Section_6 Zynq Development with System Generator & VIVADO/1. ZedBoard XADC+ Pmod Interfacing and Implementation on System Generator.mp4
65.7 MB
~Get Your Files Here !/3. Section_3 Project with System Generator/1. Section_3 Basic Project with System Generator Overview.mp4
58.3 MB
~Get Your Files Here !/2. Section_2 Introduction to HDL Coder and System Generator/1. Introduction to HDL Coder and System Generator Part I.mp4
55.8 MB
~Get Your Files Here !/1. Section_1 Installation of MatlabSimulink and VIVADOISE/2. Section 1 Lab 1 Basic Design with Simulink Environment.mp4
51.2 MB
~Get Your Files Here !/2. Section_2 Introduction to HDL Coder and System Generator/2. Introduction to HDL Coder and System Generator Part II.mp4
39.1 MB
~Get Your Files Here !/5. Section_5 Advanced Design with System Generator/1. Lab 51 FIR Filter Design.mp4
34.3 MB
~Get Your Files Here !/3. Section_3 Project with System Generator/3. Lab 31 Basic FFT Design with System Generator.mp4
33.1 MB
~Get Your Files Here !/4. Section_4 Advance Design with HDL Coder/2. LMS Filter Design_Advance Design with HDL Coder.mp4
29.4 MB
~Get Your Files Here !/5. Section_5 Advanced Design with System Generator/2. OFDM Transceiver Design and Simulation Part I Transmitter Section.mp4
19.5 MB
~Get Your Files Here !/3. Section_3 Project with System Generator/4. Lab 32 Creating Custom JTAG Configuration.mp4
18.7 MB
~Get Your Files Here !/5. Section_5 Advanced Design with System Generator/3. OFDM Transceiver Design and Simulation Part II Receiver Section & Simulation.mp4
18.6 MB
~Get Your Files Here !/3. Section_3 Project with System Generator/5. (Optional) Section_3 Lab 32 Demo JTAG Implementation on Spartan 3E from Sys Gen.mp4
11.1 MB
~Get Your Files Here !/4. Section_4 Advance Design with HDL Coder/hdl_coder_lms/original_speech.wav
4.0 MB
~Get Your Files Here !/4. Section_4 Advance Design with HDL Coder/Section-4-Advance-Design-with-HDL-Coder-with-installation-V2.pdf
3.2 MB
~Get Your Files Here !/2. Section_2 Introduction to HDL Coder and System Generator/Section-2-V2-Introduction-to-HDL-Coder-and-System-Generator.pdf
2.0 MB
~Get Your Files Here !/3. Section_3 Project with System Generator/Section-3-Basic-Project-with-System-Genrator-V2.pdf
1.3 MB
~Get Your Files Here !/1. Section_1 Installation of MatlabSimulink and VIVADOISE/Section-1-V2-Installing-Tools-Matlab-Simulink-and-ISE-VIVADO.pdf
1.1 MB
[磁力链接]
添加时间:
2021-08-30
大小:
806.4 MB
最近下载:
2025-05-07
热度:
4005
[影视]
[ FreeCourseWeb.com ] Udemy - FPGA Sort Algorithm 01
~Get Your Files Here !/01 Bubble Sort/007 Bubble Sort_07_Solution02_Simulation.mp4
75.7 MB
~Get Your Files Here !/01 Bubble Sort/003 Bubble Sort 03_Solution_01_Coding.mp4
67.6 MB
~Get Your Files Here !/03 Insertion Sort/004 Insertion Sort_04_Solution_01_Simulation.mp4
67.2 MB
~Get Your Files Here !/01 Bubble Sort/004 Bubble Sort 04_Solution_01_Simulation.mp4
66.9 MB
~Get Your Files Here !/03 Insertion Sort/003 Insertion Sort_03_Solution_01_Coding.mp4
65.9 MB
~Get Your Files Here !/03 Insertion Sort/006 Insertion Sort_06_Solution_02_Coding.mp4
61.6 MB
~Get Your Files Here !/02 Selection Sort/003 Selection Sort 03_Coding.mp4
57.9 MB
~Get Your Files Here !/02 Selection Sort/004 Selection Sort 04_Simulation.mp4
52.5 MB
~Get Your Files Here !/01 Bubble Sort/006 Bubble Sort_06_Solution02_Coding.mp4
50.1 MB
~Get Your Files Here !/03 Insertion Sort/007 Insertion_Sort_07_Solution_02_Simulation.mp4
34.6 MB
~Get Your Files Here !/02 Selection Sort/002 Selection Sort 02_Analysis.mp4
24.2 MB
~Get Your Files Here !/03 Insertion Sort/005 Insertion Sort_05_Solution_02_Analysis.mp4
20.1 MB
~Get Your Files Here !/01 Bubble Sort/005 Bubble Sort_05_Solution02_Analysis.mp4
20.1 MB
~Get Your Files Here !/01 Bubble Sort/002 Bubble Sort 02_Solution_01_Analysis.mp4
18.3 MB
~Get Your Files Here !/02 Selection Sort/001 Selection Sort 01_Introduction.mp4
9.6 MB
~Get Your Files Here !/01 Bubble Sort/001 Bubble Sort 01_Introduction.mp4
9.0 MB
~Get Your Files Here !/03 Insertion Sort/002 Insertion Sort 02_Solution_01_Analysis.mp4
8.2 MB
~Get Your Files Here !/03 Insertion Sort/001 Insertion Sort 01_Introduction.mp4
8.0 MB
~Get Your Files Here !/01 Bubble Sort/003 Bubble Sort 03_Solution_01_Coding.en.srt
12.4 kB
~Get Your Files Here !/03 Insertion Sort/003 Insertion Sort_03_Solution_01_Coding.en.srt
11.5 kB
[磁力链接]
添加时间:
2021-09-08
大小:
717.7 MB
最近下载:
2025-04-14
热度:
5016
[影视]
[ TutPig.com ] Udemy - Learn VHDL, PLS's and FPGA (Digital Electronic 2)
~Get Your Files Here !/12. Processor Design and its VHDL/1. Simple Processor Design and its VHDL.mp4
489.0 MB
~Get Your Files Here !/5. Multiplexers and Shannon Expansion/1. Multiplexers and Shannon Expansion.mp4
323.1 MB
~Get Your Files Here !/4. VHDL Adders Multiplier Narrated/1. VHDL for adders, Multiplier.mp4
308.1 MB
~Get Your Files Here !/11. VHDL code of the bus design with SWAP operation/1. VHDL code of the bus design with SWAP operation.mp4
238.9 MB
~Get Your Files Here !/3. Half Adders, Full Adders, RCA, CLA/1. HA FA RCA CLA.mp4
209.8 MB
~Get Your Files Here !/7. Conditional statement generate statement/1. Conditional statement, Generate statement, Sequential Assignment, VHDL operators.mp4
205.8 MB
~Get Your Files Here !/6. Decoders Arithmetic Comparator Selected signal assignment/1. Decoders, Arithmetic Comparator, Selected signal assignment.mp4
199.4 MB
~Get Your Files Here !/13. Modelsim/3. Modelsim Tutorial 2.mp4
198.7 MB
~Get Your Files Here !/9. VHDL gated latches flipflops, registers and counter/1. VHDL for Latches, FlipFlops, registers and counters.mp4
166.1 MB
~Get Your Files Here !/10. VHDL parallel load counters and bus design/1. Parallel Load counters and bus design.mp4
163.5 MB
~Get Your Files Here !/1. Introduction/1. Introduction to CAD tools.mp4
152.4 MB
~Get Your Files Here !/13. Modelsim/2. Modelsim Tutorial 1.mp4
134.6 MB
~Get Your Files Here !/8. latches flipflops shift and parallel access registers/1. Latches, FlipFlops, parallel access and shift registers.mp4
122.1 MB
~Get Your Files Here !/2. Numbers Representations & LUTs, PLDs, FPGA/2. LUTs, PLDs, FPGA.mp4
116.6 MB
~Get Your Files Here !/2. Numbers Representations & LUTs, PLDs, FPGA/1. Numbers Representations.mp4
93.2 MB
~Get Your Files Here !/1. Introduction/1.1 Fundamentals Of Digital Logic With VHDL Design 3rd Edition.pdf
12.8 MB
~Get Your Files Here !/4. VHDL Adders Multiplier Narrated/1.1 CENG335 Lecture 2 VHDL Adders Multiplier Narrated.pptx
3.4 MB
~Get Your Files Here !/3. Half Adders, Full Adders, RCA, CLA/1.1 CENG335 Lecture 3 HA FA RCA CLA.pptx
3.0 MB
~Get Your Files Here !/5. Multiplexers and Shannon Expansion/1.1 CENG335 Lecture 4 Multiplexers and Shannon Expansion.pptx
2.6 MB
~Get Your Files Here !/12. Processor Design and its VHDL/1.6 Exercises_set1_solution_part2.pdf
2.5 MB
[磁力链接]
添加时间:
2021-12-08
大小:
3.2 GB
最近下载:
2025-05-12
热度:
4791
[影视]
[ DevCourseWeb.com ] Udemy - FPGA (Field-Programmable Gate Array) Design and Implementation
~Get Your Files Here !/03 - FPGA Design Flows & Design Tools/001 FPGA Design Flows & Design Tools.mp4
285.8 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/009 Design Examples.mp4
226.6 MB
~Get Your Files Here !/20 - Memristive FPGA/001 Memristive FPGA.mp4
215.6 MB
~Get Your Files Here !/12 - Reconfigurable Hardware/001 Reconfigurable Hardware.mp4
209.9 MB
~Get Your Files Here !/05 - Simulate and Implement SOPC Design/001 Simulate and Implement SOPC Design.mp4
198.1 MB
~Get Your Files Here !/01 - Introduction to FPGA (Field Programmable Gate Arrays)/001 Introduction to FPGA (Field Programmable Gate Arrays).mp4
192.1 MB
~Get Your Files Here !/21 - Mentor Graphics Tools & Guidelines/001 Mentor Graphics Tools & Guidelines.mp4
184.3 MB
~Get Your Files Here !/09 - Image Processing using FPGA/001 Image Processing using FPGA.mp4
179.7 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/006 Visual Verification of Designs.mp4
165.7 MB
~Get Your Files Here !/19 - Programmable Chips and Boards/001 Programmable Chips and Boards.mp4
163.7 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/008 Finite State Machines - part 2.mp4
153.1 MB
~Get Your Files Here !/14 - FPGA implementation of DSP Circuits/001 FPGA implementation of DSP Circuits.mp4
149.7 MB
~Get Your Files Here !/15 - Reversible Logic Circuits/001 Reversible Logic Circuits.mp4
143.4 MB
~Get Your Files Here !/07 - UART SDRAM Python/001 UART SDRAM Python.mp4
132.5 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/007 Finite State Machines - part 1.mp4
132.3 MB
~Get Your Files Here !/11 - Protoflex/001 Protoflex.mp4
123.6 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/004 Procedural Assignments.mp4
119.6 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/001 Introduction to FPGA Design using Verilog.mp4
115.5 MB
~Get Your Files Here !/04 - FPGA Design using Verilog/002 Verilog overview.mp4
111.3 MB
~Get Your Files Here !/13 - Wordcount using MapReduce for FPGA/001 Wordcount using MapReduce for FPGA.mp4
109.6 MB
[磁力链接]
添加时间:
2022-03-03
大小:
4.3 GB
最近下载:
2025-05-13
热度:
7857
[影视]
[ CourseLala.com ] Udemy - FPGA Piano
~Get Your Files Here !/8. One Key Module Coding.mp4
190.6 MB
~Get Your Files Here !/2. Make Buzzer Buzzing.mp4
184.6 MB
~Get Your Files Here !/9. One Key Module Simulation.mp4
128.6 MB
~Get Your Files Here !/6. Buzzer Module Simulation.mp4
108.1 MB
~Get Your Files Here !/5. Buzzer Module Coding.mp4
101.6 MB
~Get Your Files Here !/12. Key Module Solution2 Coding.mp4
88.4 MB
~Get Your Files Here !/11. Key Module Solution1 Simultion.mp4
87.2 MB
~Get Your Files Here !/10. Key Module Solution1 Coding.mp4
74.9 MB
~Get Your Files Here !/16. LED Module Simulation.mp4
71.6 MB
~Get Your Files Here !/19. Run on Board.mp4
66.7 MB
~Get Your Files Here !/18. Top Module Simulation.mp4
66.7 MB
~Get Your Files Here !/17. Top Module Coding.mp4
59.1 MB
~Get Your Files Here !/1. System Target.mp4
57.9 MB
~Get Your Files Here !/15. LED Module Coding.mp4
48.3 MB
~Get Your Files Here !/7. Key Module Status Machine.mp4
33.3 MB
~Get Your Files Here !/13. Key Module Solution2 Simulation.mp4
23.1 MB
~Get Your Files Here !/4. Buzzer Module Status Machine.mp4
18.1 MB
~Get Your Files Here !/3. System Analysis.mp4
15.4 MB
~Get Your Files Here !/14. LED Module Status Machine.mp4
10.1 MB
~Get Your Files Here !/8. One Key Module Coding.srt
31.9 kB
[磁力链接]
添加时间:
2022-06-22
大小:
1.4 GB
最近下载:
2025-05-13
热度:
2983
[影视]
[ DevCourseWeb.com ] Udemy - Vivado 2020 - Learn Fpga Development Today!
~Get Your Files Here !/3 - VHDL/13 - Implement your design.mp4
55.5 MB
~Get Your Files Here !/5 - Processor options/20 - Testing and Simulating.mp4
51.6 MB
~Get Your Files Here !/3 - VHDL/12 - Simulating your VHDL code.mp4
48.6 MB
~Get Your Files Here !/5 - Processor options/26 - Generate HDL commands from c based code.mp4
39.2 MB
~Get Your Files Here !/5 - Processor options/24 - Implement a Micro blaze soft Processor.mp4
38.5 MB
~Get Your Files Here !/4 - Memory/19 - Creating a memory block in the integrator.mp4
36.2 MB
~Get Your Files Here !/3 - VHDL/10 - Creating your first project in Vivado.mp4
33.2 MB
~Get Your Files Here !/3 - VHDL/8 - Intro to VHDL.mp4
30.4 MB
~Get Your Files Here !/1 - Introduction/1 - The digital design fundamentals you must learn.mp4
25.8 MB
~Get Your Files Here !/2 - Digital systems/2 - Analog and Digital Systems.mp4
24.2 MB
~Get Your Files Here !/4 - Memory/17 - IP integrator in Vivado.mp4
24.0 MB
~Get Your Files Here !/5 - Processor options/25 - Learn TCL Commands to generate Micro blaze soft processor.mp4
23.8 MB
~Get Your Files Here !/2 - Digital systems/5 - Download and install Vivado.mp4
20.6 MB
~Get Your Files Here !/4 - Memory/16 - IP Flows.mp4
19.6 MB
~Get Your Files Here !/5 - Processor options/23 - Processor Options.mp4
18.3 MB
~Get Your Files Here !/4 - Memory/18 - Memory Controllers.mp4
18.1 MB
~Get Your Files Here !/6 - Conclusion/29 - Conclusion.mp4
18.0 MB
~Get Your Files Here !/3 - VHDL/9 - FPGA Design Flow.mp4
17.2 MB
~Get Your Files Here !/2 - Digital systems/4 - FPGA Architecture.mp4
17.0 MB
~Get Your Files Here !/3 - VHDL/11 - Vivado Design Tools.mp4
16.8 MB
[磁力链接]
添加时间:
2023-02-18
大小:
669.5 MB
最近下载:
2025-05-12
热度:
5302
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[CourseClub.Me] Coursera - FPGA computing systems Background knowledge and introductory materials
07_design-flows/02_xilinx-partial-reconfiguration-design-flows/05_moudle-based-vs-partial-reconfiguration-design-flows.mp4
93.3 MB
04_examples-on-how-to-configure-an-
fpga
/01_an-example-on-how-to-configure-a-clb/01_4-inputs-1-output-or-lut-configuration-example.mp4
63.8 MB
04_examples-on-how-to-configure-an-
fpga
/01_an-example-on-how-to-configure-a-clb/02_from-the-lut-to-the-clb-configuration-example.mp4
49.7 MB
05_an-introduction-to-reconfigurations/04_a-classification-of-reconfigurations/02_a-classification-of-somc-reconfigurations.mp4
42.7 MB
05_an-introduction-to-reconfigurations/04_a-classification-of-reconfigurations/01_a-classification-of-soc-reconfigurations.mp4
36.7 MB
05_an-introduction-to-reconfigurations/02_the-5-w-s/01_the-5-w-s.mp4
28.1 MB
01_a-birds-eye-view-on-adaptive-computing-systems/03_adaptive-computing-systems/05_programmable-system-on-multiple-chip.mp4
27.4 MB
03_reconfigurable-computing-and-
fpga
s/01_getting-familiar-with-
fpga
s/03_
fpga
-basic-block-interconnections.mp4
24.2 MB
03_reconfigurable-computing-and-
fpga
s/02_on-how-to-configure-an-
fpga
/04_configuration-registers.mp4
23.3 MB
03_reconfigurable-computing-and-
fpga
s/01_getting-familiar-with-
fpga
s/02_
fpga
-basic-block-clbs-and-iobs.mp4
23.3 MB
07_design-flows/02_xilinx-partial-reconfiguration-design-flows/02_xilinx-difference-based-partial-reconfiguration.mp4
22.3 MB
01_a-birds-eye-view-on-adaptive-computing-systems/02_
fpga
-and-reconfiguration/01_
fpga
-and-reconfiguration-a-1st-definition.mp4
21.9 MB
05_an-introduction-to-reconfigurations/01_a-common-vocabulary/01_a-common-vocabulary.mp4
21.1 MB
01_a-birds-eye-view-on-adaptive-computing-systems/01_class-intro/03_the-needs-for-adaptation-an-overview.mp4
20.5 MB
07_design-flows/01_xilnx-design-flows-through-years/01_xilnx-design-flows-through-years.mp4
20.4 MB
07_design-flows/02_xilinx-partial-reconfiguration-design-flows/03_xilinx-module-based-partial-reconfiguration.mp4
20.2 MB
07_design-flows/02_xilinx-partial-reconfiguration-design-flows/04_xilinx-partial-reconfiguration-pr-flow.mp4
20.0 MB
07_design-flows/02_xilinx-partial-reconfiguration-design-flows/01_partial-reconfiguration-design-flows.mp4
20.0 MB
01_a-birds-eye-view-on-adaptive-computing-systems/03_adaptive-computing-systems/04_programmable-system-on-chip.mp4
18.1 MB
02_an-introduction-to-reconfigurable-computing/01_reconfigurable-computing/04_
fpga
-based-reconfigurable-computing.mp4
15.6 MB
[磁力链接]
添加时间:
2023-02-25
大小:
762.1 MB
最近下载:
2025-05-09
热度:
3871
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[ DevCourseWeb.com ] Udemy - High-Level Synthesis For Fpga, Part 3 - Advanced
~Get Your Files Here !/6 - Pointers/35 - MultiAccess Pointers on the Interface.mp4
260.9 MB
~Get Your Files Here !/9 - HLS Stream Library/55 - Stream on the Interface.mp4
194.9 MB
~Get Your Files Here !/9 - HLS Stream Library/56 - BlockingNonBlocking.mp4
185.4 MB
~Get Your Files Here !/2 - LAB Setup/5 - Linux Installation.mp4
180.1 MB
~Get Your Files Here !/7 - AXI in HLS/44 - The maxi interface.mp4
161.8 MB
~Get Your Files Here !/3 - MultiCycle Design/14 - BlockLevel Handshake.mp4
154.1 MB
~Get Your Files Here !/6 - Pointers/34 - Pointer Arithmetic.mp4
132.5 MB
~Get Your Files Here !/6 - Pointers/31 - Definition.mp4
128.2 MB
~Get Your Files Here !/7 - AXI in HLS/40 - Memory Mapped Output 01.mp4
127.5 MB
~Get Your Files Here !/3 - MultiCycle Design/9 - Example.mp4
125.2 MB
~Get Your Files Here !/3 - MultiCycle Design/12 - Example with ack.mp4
125.0 MB
~Get Your Files Here !/4 - Streaming/21 - Streaming Example Vivado.mp4
121.5 MB
~Get Your Files Here !/7 - AXI in HLS/43 - Memory Mapped IO.mp4
116.3 MB
~Get Your Files Here !/3 - MultiCycle Design/11 - Example with vld.mp4
112.4 MB
~Get Your Files Here !/6 - Pointers/33 - Pointers on the Interface.mp4
111.2 MB
~Get Your Files Here !/8 - Loops In HLS/48 - Loop Unrolling.mp4
110.3 MB
~Get Your Files Here !/5 - ArrayInHLS/28 - Array ReadWrite Vivado.mp4
110.0 MB
~Get Your Files Here !/7 - AXI in HLS/42 - Memory Mapped Output 02.mp4
100.3 MB
~Get Your Files Here !/6 - Pointers/32 - Native Pointer Casting.mp4
95.1 MB
~Get Your Files Here !/5 - ArrayInHLS/25 - Array Issues.mp4
92.1 MB
[磁力链接]
添加时间:
2023-05-12
大小:
4.0 GB
最近下载:
2025-05-13
热度:
3263
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FPGA Piano
8. One Key Module Coding.mp4
190.6 MB
2. Make Buzzer Buzzing.mp4
184.6 MB
9. One Key Module Simulation.mp4
128.6 MB
6. Buzzer Module Simulation.mp4
108.1 MB
5. Buzzer Module Coding.mp4
101.6 MB
12. Key Module Solution2 Coding.mp4
88.4 MB
11. Key Module Solution1 Simultion.mp4
87.2 MB
10. Key Module Solution1 Coding.mp4
74.9 MB
16. LED Module Simulation.mp4
71.6 MB
19. Run on Board.mp4
66.7 MB
18. Top Module Simulation.mp4
66.7 MB
17. Top Module Coding.mp4
59.1 MB
1. System Target.mp4
57.9 MB
15. LED Module Coding.mp4
48.3 MB
7. Key Module Status Machine.mp4
33.3 MB
13. Key Module Solution2 Simulation.mp4
23.1 MB
4. Buzzer Module Status Machine.mp4
18.1 MB
3. System Analysis.mp4
15.4 MB
14. LED Module Status Machine.mp4
10.1 MB
8. One Key Module Coding.srt
31.9 kB
[磁力链接]
添加时间:
2023-07-04
大小:
1.4 GB
最近下载:
2025-05-12
热度:
4923
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FPGA Filter
2 - FPGA Median Filter/7 - FPGA Median Filter 04 Median Module Coding.mp4
95.6 MB
1 - FPGA Mean Average Filter/3 - FPGA Mean Average Filter 03 Simulation.mp4
71.7 MB
2 - FPGA Median Filter/8 - FPGA Median Filter 05 Median Module Simulation.mp4
67.3 MB
3 - FPGA Gaussian Filter/11 - FPGA Gaussian Filter 03 Simulation.mp4
67.1 MB
3 - FPGA Gaussian Filter/10 - FPGA Gaussian Filter 02 Coding.mp4
63.5 MB
2 - FPGA Median Filter/6 - FPGA Median Filter 03 Sort Module Simulation.mp4
63.1 MB
1 - FPGA Mean Average Filter/2 - FPGA Mean Average Filter 02 Coding.mp4
52.8 MB
2 - FPGA Median Filter/5 - FPGA Median Filter 02 Sort Module Coding.mp4
47.8 MB
3 - FPGA Gaussian Filter/9 - FPGA Gaussian Filter 01 Introduction.mp4
32.3 MB
2 - FPGA Median Filter/4 - FPGA Median Filter 01 Introduction.mp4
17.4 MB
1 - FPGA Mean Average Filter/1 - FPGA Mean Average Filter 01 Introduction.mp4
11.5 MB
2 - FPGA Median Filter/7 - FPGA Median Filter 04 English.vtt
13.4 kB
3 - FPGA Gaussian Filter/10 - FPGA Gaussian Filter 02 English.vtt
9.3 kB
2 - FPGA Median Filter/8 - FPGA Median Filter 05 English.vtt
7.7 kB
1 - FPGA Mean Average Filter/3 - FPGA Mean Average Filter 03 English.vtt
7.4 kB
1 - FPGA Mean Average Filter/2 - FPGA Mean Average Filter 02 English.vtt
7.2 kB
2 - FPGA Median Filter/6 - FPGA Median Filter 03 English.vtt
7.0 kB
3 - FPGA Gaussian Filter/11 - FPGA Gaussian Filter 03 English.vtt
6.8 kB
2 - FPGA Median Filter/5 - FPGA Median Filter 02 English.vtt
6.5 kB
3 - FPGA Gaussian Filter/9 - FPGA Gaussian Filter 01 English.vtt
6.3 kB
[磁力链接]
添加时间:
2023-07-14
大小:
590.2 MB
最近下载:
2025-05-13
热度:
4254
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[ DevCourseWeb.com ] Udemy - PYNQ FPGA Development with Python Programming and VIVADO
~Get Your Files Here !/6. Section 6 Creating Custom Overlay (VIVADO Project) for PYNQ/1. Creating Custom Overlay on PYNQ Addition & Multiplication Application.mp4
197.3 MB
~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/3. Section3_2 Python OpenCV Development with PYNQ FPGA Part I OpenCV Basics.mp4
152.3 MB
~Get Your Files Here !/5. Section 5 Machine Learning with Python in PYNQ/1. Machine Learning with Python.mp4
146.8 MB
~Get Your Files Here !/7. Section 7 Creating Custom Python Function Accelerator on PYNQ with VIVADO tool/1. Accelerating Custom Image Processing Function on PYNQ.mp4
145.5 MB
~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/1. Section3_0_Python_Overview.mp4
143.1 MB
~Get Your Files Here !/1. Introduction to PYNQ Architecture/1. PYNQ FPGA Introduction Part I.mp4
130.3 MB
~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/5. Python OpenCV HDMI Streaming & Processing.mp4
129.8 MB
~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/2. Section3_1 Python Programming, Conditional Statements and Loops with PYNQ GPIO.mp4
124.8 MB
~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/4. Section3_2 Python OpenCV Development with PYNQ Part II Face & Eye Detection.mp4
117.7 MB
~Get Your Files Here !/1. Introduction to PYNQ Architecture/3. Section 1 PYNQ Boards & Accessories [Demo].mp4
114.8 MB
~Get Your Files Here !/1. Introduction to PYNQ Architecture/2. PYNQ Introduction Part II.mp4
102.0 MB
~Get Your Files Here !/2. PYNQ Development Methodologies/2. PYNQ FPGA Board Setup & Basic Programming Demo.mp4
101.2 MB
~Get Your Files Here !/2. PYNQ Development Methodologies/1. PYNQ Development Methodologies Overview.mp4
98.9 MB
~Get Your Files Here !/1. Introduction to PYNQ Architecture/4. PYNQ-Z2 Unboxing and Demo [Optional].mp4
97.4 MB
~Get Your Files Here !/6. Section 6 Creating Custom Overlay (VIVADO Project) for PYNQ/3. Creating PYNQ VDMA Overlay with VIVADO 2021.1 and Python-Notebook.mp4
89.4 MB
~Get Your Files Here !/4. Section 4 Installing Python Library in PYNQ/1. Installing Cryptography Python Library on PYNQ.mp4
55.9 MB
~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/6. PYNQ-License Plate Localizer on Python OpenCV.mp4
42.9 MB
~Get Your Files Here !/6. Section 6 Creating Custom Overlay (VIVADO Project) for PYNQ/PYNQ_VDMA_Overlay_Sources_HWH_BIT_IPYNB_JPG_S9_2021/vdma/vdma.bit
4.0 MB
~Get Your Files Here !/7. Section 7 Creating Custom Python Function Accelerator on PYNQ with VIVADO tool/project_resizer/resizer.bit
4.0 MB
~Get Your Files Here !/5. Section 5 Machine Learning with Python in PYNQ/Char_Recognition_with_PYNQ_V2.ipynb
3.7 MB
[磁力链接]
添加时间:
2023-08-20
大小:
2.0 GB
最近下载:
2025-05-12
热度:
5154
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[ DevCourseWeb.com ] Udemy - Digital IC - FPGA Design P3 - Common Used Hardware Architectures
~Get Your Files Here !/2 - SRAM/1 -Behavior of SRAM and Usage Suggestions.mp4
403.5 MB
~Get Your Files Here !/4 - Pipeline Design/2 -Pipeline Design Example BIN2BCD.mp4
315.3 MB
~Get Your Files Here !/3 - Handshake Interface and Synchronous FIFO/1 -Handshake Interface and Sync_FIFO.mp4
208.8 MB
~Get Your Files Here !/4 - Pipeline Design/1 -Pipeline Fundamental.mp4
132.6 MB
~Get Your Files Here !/3 - Handshake Interface and Synchronous FIFO/2 -Depth Calculation for FIFO.mp4
109.2 MB
~Get Your Files Here !/1 - Introduction/1 -Introduction.mp4
14.9 MB
~Get Your Files Here !/Bonus Resources.txt
386 Bytes
Get Bonus Downloads Here.url
182 Bytes
[磁力链接]
添加时间:
2025-01-13
大小:
1.2 GB
最近下载:
2025-05-13
热度:
600
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[ DevCourseWeb.com ] Udemy - Hands-on development of cpu- soc on FPGA using vhdl(verilog)
~Get Your Files Here !/18 -888.mp4
461.5 MB
~Get Your Files Here !/14 -how to control memory operation, register operation, alu operation etc.mp4
304.8 MB
~Get Your Files Here !/6 -Extracting instruction set from RISC-V datasheet.mp4
261.9 MB
~Get Your Files Here !/8 -how to setup the read and write register alias table.mp4
203.3 MB
~Get Your Files Here !/7 -introducing the counter-track out-of-order execution.mp4
176.0 MB
~Get Your Files Here !/17 -the cache control.mp4
171.0 MB
~Get Your Files Here !/16 -how to setup the cache control for hit, miss, cache address and memory address.mp4
150.4 MB
~Get Your Files Here !/15 -how control handles cache misses and cache hit.mp4
128.1 MB
~Get Your Files Here !/13 -how to connect different units using the control.mp4
127.9 MB
~Get Your Files Here !/19 -top wiring and conclusion.mp4
110.6 MB
~Get Your Files Here !/3 -accessing resource file.mp4
110.4 MB
~Get Your Files Here !/9 -feedback how to return registers after instruction exec using output buffers.mp4
101.4 MB
~Get Your Files Here !/5 -how to link program memory to instruction buffer and program counter buffer.mp4
86.8 MB
~Get Your Files Here !/11 -architecture of a register bank.mp4
72.5 MB
~Get Your Files Here !/12 -how to handle multiple function units. introducing memory buffers.mp4
54.7 MB
~Get Your Files Here !/10 -How to design a simple ALU.mp4
49.2 MB
~Get Your Files Here !/2 -Architecture of the design.mp4
47.9 MB
~Get Your Files Here !/4 -How to design the program memory.mp4
39.5 MB
~Get Your Files Here !/1 -Introduction.mp4
21.2 MB
~Get Your Files Here !/3 -class_resources.zip
11.6 MB
[磁力链接]
添加时间:
2025-02-28
大小:
2.7 GB
最近下载:
2025-05-13
热度:
723
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